!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_OUTPUT_FILESEP	slash	/slash or backslash/
!_TAG_OUTPUT_MODE	u-ctags	/u-ctags or e-ctags/
!_TAG_PATTERN_LENGTH_LIMIT	96	/0 for no limit/
!_TAG_PROGRAM_AUTHOR	Universal Ctags Team	//
!_TAG_PROGRAM_NAME	Universal Ctags	/Derived from Exuberant Ctags/
!_TAG_PROGRAM_URL	https://ctags.io/	/official site/
!_TAG_PROGRAM_VERSION	0.0.0	//
ADDR	dwmac5.h	/^#define ADDR	/;"	d
ADDR_SHIFT	dwmac5.h	/^#define ADDR_SHIFT	/;"	d
AUTOINSTALL	dkms.conf	/^AUTOINSTALL="YES"$/;"	k
AUTONEGO_LINK_TIMER	altr_tse_pcs.c	/^#define AUTONEGO_LINK_TIMER	/;"	d	file:
AUTO_CAL_CONFIG	dwmac-dwc-qos-eth.c	/^#define AUTO_CAL_CONFIG /;"	d	file:
AUTO_CAL_CONFIG_ENABLE	dwmac-dwc-qos-eth.c	/^#define  AUTO_CAL_CONFIG_ENABLE /;"	d	file:
AUTO_CAL_CONFIG_START	dwmac-dwc-qos-eth.c	/^#define  AUTO_CAL_CONFIG_START /;"	d	file:
AUTO_CAL_STATUS	dwmac-dwc-qos-eth.c	/^#define AUTO_CAL_STATUS /;"	d	file:
AUTO_CAL_STATUS_ACTIVE	dwmac-dwc-qos-eth.c	/^#define  AUTO_CAL_STATUS_ACTIVE /;"	d	file:
BTR_HIGH	dwmac5.h	/^#define BTR_HIGH	/;"	d
BTR_LOW	dwmac5.h	/^#define BTR_LOW	/;"	d
BUF_SIZE_16KiB	common.h	/^#define BUF_SIZE_16KiB /;"	d
BUF_SIZE_2KiB	common.h	/^#define BUF_SIZE_2KiB /;"	d
BUF_SIZE_4KiB	common.h	/^#define BUF_SIZE_4KiB /;"	d
BUF_SIZE_8KiB	common.h	/^#define BUF_SIZE_8KiB /;"	d
CLEAN	dkms.conf	/^CLEAN="make -C ${kernel_source_dir} M=${dkms_tree}\/${PACKAGE_NAME}\/${PACKAGE_VERSION}\/build c/;"	k
CONFIG_DWMAC_ANARION	Kconfig	/^config DWMAC_ANARION$/;"	c
CONFIG_DWMAC_DWC_QOS_ETH	Kconfig	/^config DWMAC_DWC_QOS_ETH$/;"	c
CONFIG_DWMAC_GENERIC	Kconfig	/^config DWMAC_GENERIC$/;"	c
CONFIG_DWMAC_IMX8	Kconfig	/^config DWMAC_IMX8$/;"	c
CONFIG_DWMAC_INTEL	Kconfig	/^config DWMAC_INTEL$/;"	c
CONFIG_DWMAC_INTEL_PLAT	Kconfig	/^config DWMAC_INTEL_PLAT$/;"	c
CONFIG_DWMAC_IPQ806X	Kconfig	/^config DWMAC_IPQ806X$/;"	c
CONFIG_DWMAC_LPC18XX	Kconfig	/^config DWMAC_LPC18XX$/;"	c
CONFIG_DWMAC_MEDIATEK	Kconfig	/^config DWMAC_MEDIATEK$/;"	c
CONFIG_DWMAC_MESON	Kconfig	/^config DWMAC_MESON$/;"	c
CONFIG_DWMAC_OXNAS	Kconfig	/^config DWMAC_OXNAS$/;"	c
CONFIG_DWMAC_QCOM_ETHQOS	Kconfig	/^config DWMAC_QCOM_ETHQOS$/;"	c
CONFIG_DWMAC_ROCKCHIP	Kconfig	/^config DWMAC_ROCKCHIP$/;"	c
CONFIG_DWMAC_SOCFPGA	Kconfig	/^config DWMAC_SOCFPGA$/;"	c
CONFIG_DWMAC_STI	Kconfig	/^config DWMAC_STI$/;"	c
CONFIG_DWMAC_STM32	Kconfig	/^config DWMAC_STM32$/;"	c
CONFIG_DWMAC_SUN8I	Kconfig	/^config DWMAC_SUN8I$/;"	c
CONFIG_DWMAC_SUNXI	Kconfig	/^config DWMAC_SUNXI$/;"	c
CONFIG_STMMAC_ETH	Kconfig	/^config STMMAC_ETH$/;"	c
CONFIG_STMMAC_PCI	Kconfig	/^config STMMAC_PCI$/;"	c
CONFIG_STMMAC_PLATFORM	Kconfig	/^config STMMAC_PLATFORM$/;"	c
CONFIG_STMMAC_SELFTESTS	Kconfig	/^config STMMAC_SELFTESTS$/;"	c
CORE_IRQ_MTL_RX_OVERFLOW	common.h	/^#define CORE_IRQ_MTL_RX_OVERFLOW	/;"	d
CORE_IRQ_RX_PATH_EXIT_LPI_MODE	common.h	/^#define	CORE_IRQ_RX_PATH_EXIT_LPI_MODE	/;"	d
CORE_IRQ_RX_PATH_IN_LPI_MODE	common.h	/^#define	CORE_IRQ_RX_PATH_IN_LPI_MODE	/;"	d
CORE_IRQ_TX_PATH_EXIT_LPI_MODE	common.h	/^#define	CORE_IRQ_TX_PATH_EXIT_LPI_MODE	/;"	d
CORE_IRQ_TX_PATH_IN_LPI_MODE	common.h	/^#define	CORE_IRQ_TX_PATH_IN_LPI_MODE	/;"	d
CSR_F_100M	common.h	/^#define CSR_F_100M	/;"	d
CSR_F_150M	common.h	/^#define CSR_F_150M	/;"	d
CSR_F_250M	common.h	/^#define CSR_F_250M	/;"	d
CSR_F_300M	common.h	/^#define CSR_F_300M	/;"	d
CSR_F_35M	common.h	/^#define CSR_F_35M	/;"	d
CSR_F_60M	common.h	/^#define CSR_F_60M	/;"	d
CTR_HIGH	dwmac5.h	/^#define CTR_HIGH	/;"	d
CTR_LOW	dwmac5.h	/^#define CTR_LOW	/;"	d
DECIS	dwmac5.h	/^#define DECIS	/;"	d
DEFAULT_BUFSIZE	stmmac_main.c	/^#define	DEFAULT_BUFSIZE	/;"	d	file:
DEFAULT_DMA_PBL	common.h	/^#define DEFAULT_DMA_PBL	/;"	d
DEF_DMA_RIWT	common.h	/^#define DEF_DMA_RIWT	/;"	d
DELAY_ENABLE	dwmac-rk.c	/^#define DELAY_ENABLE(/;"	d	file:
DEUIS	dwmac5.h	/^#define DEUIS	/;"	d
DMA_AXI_1KBBE	dwmac4_dma.h	/^#define DMA_AXI_1KBBE	/;"	d
DMA_AXI_1KBBE	dwmac_dma.h	/^#define	DMA_AXI_1KBBE	/;"	d
DMA_AXI_AAL	dwmac_dma.h	/^#define DMA_AXI_AAL	/;"	d
DMA_AXI_BLEN128	dwmac4_dma.h	/^#define DMA_AXI_BLEN128	/;"	d
DMA_AXI_BLEN128	dwmac_dma.h	/^#define DMA_AXI_BLEN128	/;"	d
DMA_AXI_BLEN16	dwmac4_dma.h	/^#define DMA_AXI_BLEN16	/;"	d
DMA_AXI_BLEN16	dwmac_dma.h	/^#define DMA_AXI_BLEN16	/;"	d
DMA_AXI_BLEN256	dwmac4_dma.h	/^#define DMA_AXI_BLEN256	/;"	d
DMA_AXI_BLEN256	dwmac_dma.h	/^#define DMA_AXI_BLEN256	/;"	d
DMA_AXI_BLEN32	dwmac4_dma.h	/^#define DMA_AXI_BLEN32	/;"	d
DMA_AXI_BLEN32	dwmac_dma.h	/^#define DMA_AXI_BLEN32	/;"	d
DMA_AXI_BLEN4	dwmac4_dma.h	/^#define DMA_AXI_BLEN4	/;"	d
DMA_AXI_BLEN4	dwmac_dma.h	/^#define DMA_AXI_BLEN4	/;"	d
DMA_AXI_BLEN64	dwmac4_dma.h	/^#define DMA_AXI_BLEN64	/;"	d
DMA_AXI_BLEN64	dwmac_dma.h	/^#define DMA_AXI_BLEN64	/;"	d
DMA_AXI_BLEN8	dwmac4_dma.h	/^#define DMA_AXI_BLEN8	/;"	d
DMA_AXI_BLEN8	dwmac_dma.h	/^#define DMA_AXI_BLEN8	/;"	d
DMA_AXI_BURST_LEN_MASK	dwmac4_dma.h	/^#define DMA_AXI_BURST_LEN_MASK	/;"	d
DMA_AXI_BURST_LEN_MASK	dwmac_dma.h	/^#define DMA_AXI_BURST_LEN_MASK	/;"	d
DMA_AXI_BUS_MODE	dwmac4_dma.h	/^#define DMA_AXI_BUS_MODE	/;"	d
DMA_AXI_BUS_MODE	dwmac_dma.h	/^#define DMA_AXI_BUS_MODE	/;"	d
DMA_AXI_EN_LPI	dwmac4_dma.h	/^#define DMA_AXI_EN_LPI	/;"	d
DMA_AXI_EN_LPI	dwmac_dma.h	/^#define DMA_AXI_EN_LPI	/;"	d
DMA_AXI_LPI_XIT_FRM	dwmac4_dma.h	/^#define DMA_AXI_LPI_XIT_FRM	/;"	d
DMA_AXI_LPI_XIT_FRM	dwmac_dma.h	/^#define DMA_AXI_LPI_XIT_FRM	/;"	d
DMA_AXI_MAX_OSR_LIMIT	dwmac4_dma.h	/^#define DMA_AXI_MAX_OSR_LIMIT /;"	d
DMA_AXI_MAX_OSR_LIMIT	dwmac_dma.h	/^#define DMA_AXI_MAX_OSR_LIMIT /;"	d
DMA_AXI_OSR_MAX	dwmac4_dma.h	/^#define DMA_AXI_OSR_MAX	/;"	d
DMA_AXI_OSR_MAX	dwmac_dma.h	/^#define DMA_AXI_OSR_MAX	/;"	d
DMA_AXI_RD_OSR_LMT	dwmac4_dma.h	/^#define DMA_AXI_RD_OSR_LMT	/;"	d
DMA_AXI_RD_OSR_LMT	dwmac_dma.h	/^#define DMA_AXI_RD_OSR_LMT	/;"	d
DMA_AXI_RD_OSR_LMT_MASK	dwmac_dma.h	/^#define DMA_AXI_RD_OSR_LMT_MASK	/;"	d
DMA_AXI_RD_OSR_LMT_SHIFT	dwmac4_dma.h	/^#define DMA_AXI_RD_OSR_LMT_SHIFT	/;"	d
DMA_AXI_RD_OSR_LMT_SHIFT	dwmac_dma.h	/^#define DMA_AXI_RD_OSR_LMT_SHIFT	/;"	d
DMA_AXI_UNDEF	dwmac_dma.h	/^#define DMA_AXI_UNDEF	/;"	d
DMA_AXI_WR_OSR_LMT	dwmac4_dma.h	/^#define DMA_AXI_WR_OSR_LMT	/;"	d
DMA_AXI_WR_OSR_LMT	dwmac_dma.h	/^#define DMA_AXI_WR_OSR_LMT	/;"	d
DMA_AXI_WR_OSR_LMT_MASK	dwmac_dma.h	/^#define DMA_AXI_WR_OSR_LMT_MASK	/;"	d
DMA_AXI_WR_OSR_LMT_SHIFT	dwmac4_dma.h	/^#define DMA_AXI_WR_OSR_LMT_SHIFT	/;"	d
DMA_AXI_WR_OSR_LMT_SHIFT	dwmac_dma.h	/^#define DMA_AXI_WR_OSR_LMT_SHIFT	/;"	d
DMA_BURST_LEN_DEFAULT	dwmac4_dma.h	/^#define DMA_BURST_LEN_DEFAULT	/;"	d
DMA_BURST_LEN_DEFAULT	dwmac_dma.h	/^#define DMA_BURST_LEN_DEFAULT	/;"	d
DMA_BUS_FB	dwmac1000.h	/^#define DMA_BUS_FB	/;"	d
DMA_BUS_MODE	dwmac4_dma.h	/^#define DMA_BUS_MODE	/;"	d
DMA_BUS_MODE	dwmac_dma.h	/^#define DMA_BUS_MODE	/;"	d
DMA_BUS_MODE_AAL	dwmac1000.h	/^#define DMA_BUS_MODE_AAL	/;"	d
DMA_BUS_MODE_ATDS	dwmac1000.h	/^#define DMA_BUS_MODE_ATDS	/;"	d
DMA_BUS_MODE_BAR_BUS	dwmac100.h	/^#define DMA_BUS_MODE_BAR_BUS	/;"	d
DMA_BUS_MODE_BLE	dwmac100.h	/^#define DMA_BUS_MODE_BLE	/;"	d
DMA_BUS_MODE_DA	dwmac1000.h	/^#define DMA_BUS_MODE_DA	/;"	d
DMA_BUS_MODE_DBO	dwmac100.h	/^#define DMA_BUS_MODE_DBO	/;"	d
DMA_BUS_MODE_DEFAULT	dwmac100.h	/^#define DMA_BUS_MODE_DEFAULT	/;"	d
DMA_BUS_MODE_DSL_MASK	dwmac100.h	/^#define DMA_BUS_MODE_DSL_MASK	/;"	d
DMA_BUS_MODE_DSL_MASK	dwmac1000.h	/^#define DMA_BUS_MODE_DSL_MASK	/;"	d
DMA_BUS_MODE_DSL_SHIFT	dwmac100.h	/^#define DMA_BUS_MODE_DSL_SHIFT	/;"	d
DMA_BUS_MODE_DSL_SHIFT	dwmac1000.h	/^#define DMA_BUS_MODE_DSL_SHIFT	/;"	d
DMA_BUS_MODE_FB	dwmac1000.h	/^#define DMA_BUS_MODE_FB	/;"	d
DMA_BUS_MODE_FB	dwmac4_dma.h	/^#define DMA_BUS_MODE_FB	/;"	d
DMA_BUS_MODE_MAXPBL	dwmac1000.h	/^#define DMA_BUS_MODE_MAXPBL	/;"	d
DMA_BUS_MODE_MB	dwmac1000.h	/^#define DMA_BUS_MODE_MB	/;"	d
DMA_BUS_MODE_MB	dwmac4_dma.h	/^#define DMA_BUS_MODE_MB	/;"	d
DMA_BUS_MODE_PBL	dwmac4_dma.h	/^#define DMA_BUS_MODE_PBL	/;"	d
DMA_BUS_MODE_PBL_MASK	dwmac100.h	/^#define DMA_BUS_MODE_PBL_MASK	/;"	d
DMA_BUS_MODE_PBL_MASK	dwmac1000.h	/^#define DMA_BUS_MODE_PBL_MASK	/;"	d
DMA_BUS_MODE_PBL_SHIFT	dwmac100.h	/^#define DMA_BUS_MODE_PBL_SHIFT	/;"	d
DMA_BUS_MODE_PBL_SHIFT	dwmac1000.h	/^#define DMA_BUS_MODE_PBL_SHIFT	/;"	d
DMA_BUS_MODE_PBL_SHIFT	dwmac4_dma.h	/^#define DMA_BUS_MODE_PBL_SHIFT	/;"	d
DMA_BUS_MODE_RPBL_MASK	dwmac1000.h	/^#define DMA_BUS_MODE_RPBL_MASK	/;"	d
DMA_BUS_MODE_RPBL_SHIFT	dwmac1000.h	/^#define DMA_BUS_MODE_RPBL_SHIFT	/;"	d
DMA_BUS_MODE_RPBL_SHIFT	dwmac4_dma.h	/^#define DMA_BUS_MODE_RPBL_SHIFT	/;"	d
DMA_BUS_MODE_SFT_RESET	dwmac4_dma.h	/^#define DMA_BUS_MODE_SFT_RESET	/;"	d
DMA_BUS_MODE_SFT_RESET	dwmac_dma.h	/^#define DMA_BUS_MODE_SFT_RESET	/;"	d
DMA_BUS_MODE_SPH	dwmac4_dma.h	/^#define DMA_BUS_MODE_SPH	/;"	d
DMA_BUS_MODE_USP	dwmac1000.h	/^#define DMA_BUS_MODE_USP	/;"	d
DMA_BUS_PR_RATIO_MASK	dwmac1000.h	/^#define DMA_BUS_PR_RATIO_MASK	/;"	d
DMA_BUS_PR_RATIO_SHIFT	dwmac1000.h	/^#define DMA_BUS_PR_RATIO_SHIFT	/;"	d
DMA_CHAN0_DBG_STAT_RPS	dwmac4_dma.h	/^#define DMA_CHAN0_DBG_STAT_RPS	/;"	d
DMA_CHAN0_DBG_STAT_RPS_SHIFT	dwmac4_dma.h	/^#define DMA_CHAN0_DBG_STAT_RPS_SHIFT	/;"	d
DMA_CHAN0_DBG_STAT_TPS	dwmac4_dma.h	/^#define DMA_CHAN0_DBG_STAT_TPS	/;"	d
DMA_CHAN0_DBG_STAT_TPS_SHIFT	dwmac4_dma.h	/^#define DMA_CHAN0_DBG_STAT_TPS_SHIFT	/;"	d
DMA_CHANNEL_NB_MAX	dwmac4_dma.h	/^#define DMA_CHANNEL_NB_MAX	/;"	d
DMA_CHANX_BASE_ADDR	dwmac4_dma.h	/^#define DMA_CHANX_BASE_ADDR(/;"	d
DMA_CHAN_BASE_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_BASE_ADDR	/;"	d
DMA_CHAN_BASE_OFFSET	dwmac4_dma.h	/^#define DMA_CHAN_BASE_OFFSET	/;"	d
DMA_CHAN_CONTROL	dwmac4_dma.h	/^#define DMA_CHAN_CONTROL(/;"	d
DMA_CHAN_CUR_RX_BUF_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_CUR_RX_BUF_ADDR(/;"	d
DMA_CHAN_CUR_RX_DESC	dwmac4_dma.h	/^#define DMA_CHAN_CUR_RX_DESC(/;"	d
DMA_CHAN_CUR_TX_BUF_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_CUR_TX_BUF_ADDR(/;"	d
DMA_CHAN_CUR_TX_DESC	dwmac4_dma.h	/^#define DMA_CHAN_CUR_TX_DESC(/;"	d
DMA_CHAN_INTR_ABNORMAL	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ABNORMAL	/;"	d
DMA_CHAN_INTR_ABNORMAL_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ABNORMAL_4_10	/;"	d
DMA_CHAN_INTR_DEFAULT_MASK	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_MASK	/;"	d
DMA_CHAN_INTR_DEFAULT_MASK_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_MASK_4_10	/;"	d
DMA_CHAN_INTR_DEFAULT_RX	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_RX	/;"	d
DMA_CHAN_INTR_DEFAULT_RX_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_RX_4_10	/;"	d
DMA_CHAN_INTR_DEFAULT_TX	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_TX	/;"	d
DMA_CHAN_INTR_DEFAULT_TX_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_DEFAULT_TX_4_10	/;"	d
DMA_CHAN_INTR_ENA	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA(/;"	d
DMA_CHAN_INTR_ENA_AIE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_AIE	/;"	d
DMA_CHAN_INTR_ENA_AIE_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_AIE_4_10	/;"	d
DMA_CHAN_INTR_ENA_CDE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_CDE	/;"	d
DMA_CHAN_INTR_ENA_ERE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_ERE	/;"	d
DMA_CHAN_INTR_ENA_ETE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_ETE	/;"	d
DMA_CHAN_INTR_ENA_FBE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_FBE	/;"	d
DMA_CHAN_INTR_ENA_NIE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_NIE	/;"	d
DMA_CHAN_INTR_ENA_NIE_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_NIE_4_10	/;"	d
DMA_CHAN_INTR_ENA_RBUE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_RBUE	/;"	d
DMA_CHAN_INTR_ENA_RIE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_RIE	/;"	d
DMA_CHAN_INTR_ENA_RSE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_RSE	/;"	d
DMA_CHAN_INTR_ENA_RWE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_RWE	/;"	d
DMA_CHAN_INTR_ENA_TBUE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_TBUE	/;"	d
DMA_CHAN_INTR_ENA_TIE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_TIE	/;"	d
DMA_CHAN_INTR_ENA_TSE	dwmac4_dma.h	/^#define DMA_CHAN_INTR_ENA_TSE	/;"	d
DMA_CHAN_INTR_NORMAL	dwmac4_dma.h	/^#define DMA_CHAN_INTR_NORMAL	/;"	d
DMA_CHAN_INTR_NORMAL_4_10	dwmac4_dma.h	/^#define DMA_CHAN_INTR_NORMAL_4_10	/;"	d
DMA_CHAN_REG_NUMBER	dwmac4_dma.h	/^#define DMA_CHAN_REG_NUMBER	/;"	d
DMA_CHAN_RX_BASE_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_RX_BASE_ADDR(/;"	d
DMA_CHAN_RX_BASE_ADDR_HI	dwmac4_dma.h	/^#define DMA_CHAN_RX_BASE_ADDR_HI(/;"	d
DMA_CHAN_RX_CONTROL	dwmac4_dma.h	/^#define DMA_CHAN_RX_CONTROL(/;"	d
DMA_CHAN_RX_END_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_RX_END_ADDR(/;"	d
DMA_CHAN_RX_RING_LEN	dwmac4_dma.h	/^#define DMA_CHAN_RX_RING_LEN(/;"	d
DMA_CHAN_RX_WATCHDOG	dwmac4_dma.h	/^#define DMA_CHAN_RX_WATCHDOG(/;"	d
DMA_CHAN_SLOT_CTRL_STATUS	dwmac4_dma.h	/^#define DMA_CHAN_SLOT_CTRL_STATUS(/;"	d
DMA_CHAN_STATUS	dwmac4_dma.h	/^#define DMA_CHAN_STATUS(/;"	d
DMA_CHAN_STATUS_AIS	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_AIS	/;"	d
DMA_CHAN_STATUS_CDE	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_CDE	/;"	d
DMA_CHAN_STATUS_ERI	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_ERI	/;"	d
DMA_CHAN_STATUS_ETI	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_ETI	/;"	d
DMA_CHAN_STATUS_FBE	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_FBE	/;"	d
DMA_CHAN_STATUS_NIS	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_NIS	/;"	d
DMA_CHAN_STATUS_RBU	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_RBU	/;"	d
DMA_CHAN_STATUS_REB	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_REB	/;"	d
DMA_CHAN_STATUS_REB_SHIFT	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_REB_SHIFT	/;"	d
DMA_CHAN_STATUS_RI	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_RI	/;"	d
DMA_CHAN_STATUS_RPS	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_RPS	/;"	d
DMA_CHAN_STATUS_RWT	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_RWT	/;"	d
DMA_CHAN_STATUS_TBU	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_TBU	/;"	d
DMA_CHAN_STATUS_TEB	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_TEB	/;"	d
DMA_CHAN_STATUS_TEB_SHIFT	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_TEB_SHIFT	/;"	d
DMA_CHAN_STATUS_TI	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_TI	/;"	d
DMA_CHAN_STATUS_TPS	dwmac4_dma.h	/^#define DMA_CHAN_STATUS_TPS	/;"	d
DMA_CHAN_TX_BASE_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_TX_BASE_ADDR(/;"	d
DMA_CHAN_TX_BASE_ADDR_HI	dwmac4_dma.h	/^#define DMA_CHAN_TX_BASE_ADDR_HI(/;"	d
DMA_CHAN_TX_CONTROL	dwmac4_dma.h	/^#define DMA_CHAN_TX_CONTROL(/;"	d
DMA_CHAN_TX_END_ADDR	dwmac4_dma.h	/^#define DMA_CHAN_TX_END_ADDR(/;"	d
DMA_CHAN_TX_RING_LEN	dwmac4_dma.h	/^#define DMA_CHAN_TX_RING_LEN(/;"	d
DMA_CONTROL	dwmac_dma.h	/^#define DMA_CONTROL	/;"	d
DMA_CONTROL_DFF	dwmac1000.h	/^#define DMA_CONTROL_DFF	/;"	d
DMA_CONTROL_DT	dwmac1000.h	/^#define DMA_CONTROL_DT	/;"	d
DMA_CONTROL_EDSE	dwmac4_dma.h	/^#define DMA_CONTROL_EDSE	/;"	d
DMA_CONTROL_EFC	dwmac1000.h	/^#define DMA_CONTROL_EFC	/;"	d
DMA_CONTROL_FEF	dwmac1000.h	/^#define DMA_CONTROL_FEF	/;"	d
DMA_CONTROL_FTF	dwmac_dma.h	/^#define DMA_CONTROL_FTF	/;"	d
DMA_CONTROL_FUF	dwmac1000.h	/^#define DMA_CONTROL_FUF	/;"	d
DMA_CONTROL_MSS_MASK	dwmac4_dma.h	/^#define DMA_CONTROL_MSS_MASK	/;"	d
DMA_CONTROL_OSF	dwmac100.h	/^	DMA_CONTROL_OSF = 0x00000004,	\/* Operate On 2nd Frame *\/$/;"	e	enum:ttc_control
DMA_CONTROL_OSF	dwmac1000.h	/^#define DMA_CONTROL_OSF	/;"	d
DMA_CONTROL_OSP	dwmac4_dma.h	/^#define DMA_CONTROL_OSP	/;"	d
DMA_CONTROL_RFA_MASK	dwmac1000.h	/^#define DMA_CONTROL_RFA_MASK	/;"	d
DMA_CONTROL_RFD_MASK	dwmac1000.h	/^#define DMA_CONTROL_RFD_MASK	/;"	d
DMA_CONTROL_RSF	dwmac1000.h	/^#define DMA_CONTROL_RSF	/;"	d
DMA_CONTROL_RTC_128	dwmac1000.h	/^	DMA_CONTROL_RTC_128 = 0x00000018,$/;"	e	enum:rtc_control
DMA_CONTROL_RTC_32	dwmac1000.h	/^	DMA_CONTROL_RTC_32 = 0x00000008,$/;"	e	enum:rtc_control
DMA_CONTROL_RTC_64	dwmac1000.h	/^	DMA_CONTROL_RTC_64 = 0x00000000,$/;"	e	enum:rtc_control
DMA_CONTROL_RTC_96	dwmac1000.h	/^	DMA_CONTROL_RTC_96 = 0x00000010,$/;"	e	enum:rtc_control
DMA_CONTROL_SE	dwmac100.h	/^	DMA_CONTROL_SE = 0x00000008,	\/* Stop On Empty *\/$/;"	e	enum:ttc_control
DMA_CONTROL_SF	dwmac100.h	/^#define DMA_CONTROL_SF	/;"	d
DMA_CONTROL_SPH	dwmac4_dma.h	/^#define DMA_CONTROL_SPH	/;"	d
DMA_CONTROL_SR	dwmac4_dma.h	/^#define DMA_CONTROL_SR	/;"	d
DMA_CONTROL_SR	dwmac_dma.h	/^#define DMA_CONTROL_SR	/;"	d
DMA_CONTROL_ST	dwmac4_dma.h	/^#define DMA_CONTROL_ST	/;"	d
DMA_CONTROL_ST	dwmac_dma.h	/^#define DMA_CONTROL_ST	/;"	d
DMA_CONTROL_TC_RX_MASK	dwmac1000.h	/^#define DMA_CONTROL_TC_RX_MASK	/;"	d
DMA_CONTROL_TC_TX_MASK	dwmac1000.h	/^#define DMA_CONTROL_TC_TX_MASK	/;"	d
DMA_CONTROL_TSE	dwmac4_dma.h	/^#define DMA_CONTROL_TSE	/;"	d
DMA_CONTROL_TSF	dwmac1000.h	/^#define DMA_CONTROL_TSF	/;"	d
DMA_CONTROL_TTC_128	dwmac100.h	/^	DMA_CONTROL_TTC_128 = 0x00008000,	\/* Threshold is 128 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_128	dwmac1000.h	/^	DMA_CONTROL_TTC_128 = 0x00004000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_16	dwmac1000.h	/^	DMA_CONTROL_TTC_16 = 0x0001c000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_18	dwmac100.h	/^	DMA_CONTROL_TTC_18 = 0x00400000,	\/* Threshold is 18 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_192	dwmac1000.h	/^	DMA_CONTROL_TTC_192 = 0x00008000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_24	dwmac100.h	/^	DMA_CONTROL_TTC_24 = 0x00404000,	\/* Threshold is 24 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_24	dwmac1000.h	/^	DMA_CONTROL_TTC_24 = 0x00018000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_256	dwmac100.h	/^	DMA_CONTROL_TTC_256 = 0x0000c000,	\/* Threshold is 256 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_256	dwmac1000.h	/^	DMA_CONTROL_TTC_256 = 0x0000c000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_32	dwmac100.h	/^	DMA_CONTROL_TTC_32 = 0x00408000,	\/* Threshold is 32 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_32	dwmac1000.h	/^	DMA_CONTROL_TTC_32 = 0x00014000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_40	dwmac100.h	/^	DMA_CONTROL_TTC_40 = 0x0040c000,	\/* Threshold is 40 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_40	dwmac1000.h	/^	DMA_CONTROL_TTC_40 = 0x00010000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_64	dwmac100.h	/^	DMA_CONTROL_TTC_64 = 0x00004000,	\/* Threshold is 64 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_64	dwmac1000.h	/^	DMA_CONTROL_TTC_64 = 0x00000000,$/;"	e	enum:ttc_control
DMA_CONTROL_TTC_DEFAULT	dwmac100.h	/^	DMA_CONTROL_TTC_DEFAULT = 0x00000000,	\/* Threshold is 32 DWORDS *\/$/;"	e	enum:ttc_control
DMA_CUR_RX_BUF_ADDR	dwmac_dma.h	/^#define DMA_CUR_RX_BUF_ADDR	/;"	d
DMA_CUR_TX_BUF_ADDR	dwmac_dma.h	/^#define DMA_CUR_TX_BUF_ADDR	/;"	d
DMA_DEBUG_STATUS_0	dwmac4_dma.h	/^#define DMA_DEBUG_STATUS_0	/;"	d
DMA_DEBUG_STATUS_1	dwmac4_dma.h	/^#define DMA_DEBUG_STATUS_1	/;"	d
DMA_DEBUG_STATUS_2	dwmac4_dma.h	/^#define DMA_DEBUG_STATUS_2	/;"	d
DMA_DEBUG_STATUS_RS_MASK	dwmac4_dma.h	/^#define DMA_DEBUG_STATUS_RS_MASK	/;"	d
DMA_DEBUG_STATUS_TS_MASK	dwmac4_dma.h	/^#define DMA_DEBUG_STATUS_TS_MASK	/;"	d
DMA_DEFAULT_RX_SIZE	common.h	/^#define DMA_DEFAULT_RX_SIZE	/;"	d
DMA_DEFAULT_TX_SIZE	common.h	/^#define DMA_DEFAULT_TX_SIZE	/;"	d
DMA_ECC_INT_ENABLE	dwmac5.h	/^#define DMA_ECC_INT_ENABLE	/;"	d
DMA_ECC_INT_STATUS	dwmac5.h	/^#define DMA_ECC_INT_STATUS	/;"	d
DMA_HOST_RX_DESC	dwmac1000.h	/^#define DMA_HOST_RX_DESC	/;"	d
DMA_HOST_TX_DESC	dwmac1000.h	/^#define DMA_HOST_TX_DESC	/;"	d
DMA_HW_FEATURE	dwmac_dma.h	/^#define DMA_HW_FEATURE	/;"	d
DMA_HW_FEAT_ACTPHYIF	common.h	/^#define DMA_HW_FEAT_ACTPHYIF	/;"	d
DMA_HW_FEAT_ADDMAC	common.h	/^#define DMA_HW_FEAT_ADDMAC	/;"	d
DMA_HW_FEAT_AVSEL	common.h	/^#define DMA_HW_FEAT_AVSEL	/;"	d
DMA_HW_FEAT_EEESEL	common.h	/^#define DMA_HW_FEAT_EEESEL	/;"	d
DMA_HW_FEAT_ENHDESSEL	common.h	/^#define DMA_HW_FEAT_ENHDESSEL	/;"	d
DMA_HW_FEAT_EXTHASHEN	common.h	/^#define DMA_HW_FEAT_EXTHASHEN	/;"	d
DMA_HW_FEAT_FLEXIPPSEN	common.h	/^#define DMA_HW_FEAT_FLEXIPPSEN	/;"	d
DMA_HW_FEAT_GMIISEL	common.h	/^#define DMA_HW_FEAT_GMIISEL	/;"	d
DMA_HW_FEAT_HASHSEL	common.h	/^#define DMA_HW_FEAT_HASHSEL	/;"	d
DMA_HW_FEAT_HDSEL	common.h	/^#define DMA_HW_FEAT_HDSEL	/;"	d
DMA_HW_FEAT_INTTSEN	common.h	/^#define DMA_HW_FEAT_INTTSEN	/;"	d
DMA_HW_FEAT_L3L4FLTREN	common.h	/^#define DMA_HW_FEAT_L3L4FLTREN	/;"	d
DMA_HW_FEAT_MGKSEL	common.h	/^#define DMA_HW_FEAT_MGKSEL	/;"	d
DMA_HW_FEAT_MIISEL	common.h	/^#define DMA_HW_FEAT_MIISEL	/;"	d
DMA_HW_FEAT_MMCSEL	common.h	/^#define DMA_HW_FEAT_MMCSEL	/;"	d
DMA_HW_FEAT_PCSSEL	common.h	/^#define DMA_HW_FEAT_PCSSEL	/;"	d
DMA_HW_FEAT_RWKSEL	common.h	/^#define DMA_HW_FEAT_RWKSEL	/;"	d
DMA_HW_FEAT_RXCHCNT	common.h	/^#define DMA_HW_FEAT_RXCHCNT	/;"	d
DMA_HW_FEAT_RXFIFOSIZE	common.h	/^#define DMA_HW_FEAT_RXFIFOSIZE	/;"	d
DMA_HW_FEAT_RXTYP1COE	common.h	/^#define DMA_HW_FEAT_RXTYP1COE	/;"	d
DMA_HW_FEAT_RXTYP2COE	common.h	/^#define DMA_HW_FEAT_RXTYP2COE	/;"	d
DMA_HW_FEAT_SAVLANINS	common.h	/^#define DMA_HW_FEAT_SAVLANINS	/;"	d
DMA_HW_FEAT_SMASEL	common.h	/^#define DMA_HW_FEAT_SMASEL	/;"	d
DMA_HW_FEAT_TSVER1SEL	common.h	/^#define DMA_HW_FEAT_TSVER1SEL	/;"	d
DMA_HW_FEAT_TSVER2SEL	common.h	/^#define DMA_HW_FEAT_TSVER2SEL	/;"	d
DMA_HW_FEAT_TXCHCNT	common.h	/^#define DMA_HW_FEAT_TXCHCNT	/;"	d
DMA_HW_FEAT_TXCOESEL	common.h	/^#define DMA_HW_FEAT_TXCOESEL	/;"	d
DMA_INTR_ABNORMAL	dwmac_dma.h	/^#define DMA_INTR_ABNORMAL	/;"	d
DMA_INTR_DEFAULT_MASK	dwmac_dma.h	/^#define DMA_INTR_DEFAULT_MASK	/;"	d
DMA_INTR_DEFAULT_RX	dwmac_dma.h	/^#define DMA_INTR_DEFAULT_RX	/;"	d
DMA_INTR_DEFAULT_TX	dwmac_dma.h	/^#define DMA_INTR_DEFAULT_TX	/;"	d
DMA_INTR_ENA	dwmac_dma.h	/^#define DMA_INTR_ENA	/;"	d
DMA_INTR_ENA_AIE	dwmac_dma.h	/^#define DMA_INTR_ENA_AIE /;"	d
DMA_INTR_ENA_ERE	dwmac_dma.h	/^#define DMA_INTR_ENA_ERE /;"	d
DMA_INTR_ENA_ETE	dwmac_dma.h	/^#define DMA_INTR_ENA_ETE /;"	d
DMA_INTR_ENA_FBE	dwmac_dma.h	/^#define DMA_INTR_ENA_FBE /;"	d
DMA_INTR_ENA_NIE	dwmac_dma.h	/^#define DMA_INTR_ENA_NIE /;"	d
DMA_INTR_ENA_OVE	dwmac_dma.h	/^#define DMA_INTR_ENA_OVE /;"	d
DMA_INTR_ENA_RIE	dwmac_dma.h	/^#define DMA_INTR_ENA_RIE /;"	d
DMA_INTR_ENA_RSE	dwmac_dma.h	/^#define DMA_INTR_ENA_RSE /;"	d
DMA_INTR_ENA_RUE	dwmac_dma.h	/^#define DMA_INTR_ENA_RUE /;"	d
DMA_INTR_ENA_RWE	dwmac_dma.h	/^#define DMA_INTR_ENA_RWE /;"	d
DMA_INTR_ENA_TIE	dwmac_dma.h	/^#define DMA_INTR_ENA_TIE /;"	d
DMA_INTR_ENA_TJE	dwmac_dma.h	/^#define DMA_INTR_ENA_TJE /;"	d
DMA_INTR_ENA_TSE	dwmac_dma.h	/^#define DMA_INTR_ENA_TSE /;"	d
DMA_INTR_ENA_TUE	dwmac_dma.h	/^#define DMA_INTR_ENA_TUE /;"	d
DMA_INTR_ENA_UNE	dwmac_dma.h	/^#define DMA_INTR_ENA_UNE /;"	d
DMA_INTR_NORMAL	dwmac_dma.h	/^#define DMA_INTR_NORMAL	/;"	d
DMA_MAX_RX_SIZE	common.h	/^#define DMA_MAX_RX_SIZE	/;"	d
DMA_MAX_TX_SIZE	common.h	/^#define DMA_MAX_TX_SIZE	/;"	d
DMA_MIN_RX_SIZE	common.h	/^#define DMA_MIN_RX_SIZE	/;"	d
DMA_MIN_TX_SIZE	common.h	/^#define DMA_MIN_TX_SIZE	/;"	d
DMA_MISSED_FRAME_CTR	dwmac_dma.h	/^#define DMA_MISSED_FRAME_CTR	/;"	d
DMA_MISSED_FRAME_M_CNTR	dwmac100.h	/^#define DMA_MISSED_FRAME_M_CNTR	/;"	d
DMA_MISSED_FRAME_OVE	dwmac100.h	/^#define DMA_MISSED_FRAME_OVE	/;"	d
DMA_MISSED_FRAME_OVE_CNTR	dwmac100.h	/^#define DMA_MISSED_FRAME_OVE_CNTR /;"	d
DMA_MISSED_FRAME_OVE_M	dwmac100.h	/^#define DMA_MISSED_FRAME_OVE_M	/;"	d
DMA_RBSZ_MASK	dwmac4_dma.h	/^#define DMA_RBSZ_MASK	/;"	d
DMA_RBSZ_SHIFT	dwmac4_dma.h	/^#define DMA_RBSZ_SHIFT	/;"	d
DMA_RCV_BASE_ADDR	dwmac_dma.h	/^#define DMA_RCV_BASE_ADDR	/;"	d
DMA_RCV_POLL_DEMAND	dwmac_dma.h	/^#define DMA_RCV_POLL_DEMAND	/;"	d
DMA_RX_WATCHDOG	dwmac_dma.h	/^#define DMA_RX_WATCHDOG	/;"	d
DMA_SAFETY_INT_STATUS	dwmac5.h	/^#define DMA_SAFETY_INT_STATUS	/;"	d
DMA_STATUS	dwmac4_dma.h	/^#define DMA_STATUS	/;"	d
DMA_STATUS	dwmac_dma.h	/^#define DMA_STATUS	/;"	d
DMA_STATUS_AIS	dwmac_dma.h	/^#define DMA_STATUS_AIS	/;"	d
DMA_STATUS_CHAN0	dwmac4_dma.h	/^#define DMA_STATUS_CHAN0	/;"	d
DMA_STATUS_CHAN1	dwmac4_dma.h	/^#define DMA_STATUS_CHAN1	/;"	d
DMA_STATUS_CHAN2	dwmac4_dma.h	/^#define DMA_STATUS_CHAN2	/;"	d
DMA_STATUS_CHAN3	dwmac4_dma.h	/^#define DMA_STATUS_CHAN3	/;"	d
DMA_STATUS_CHAN4	dwmac4_dma.h	/^#define DMA_STATUS_CHAN4	/;"	d
DMA_STATUS_CHAN5	dwmac4_dma.h	/^#define DMA_STATUS_CHAN5	/;"	d
DMA_STATUS_CHAN6	dwmac4_dma.h	/^#define DMA_STATUS_CHAN6	/;"	d
DMA_STATUS_CHAN7	dwmac4_dma.h	/^#define DMA_STATUS_CHAN7	/;"	d
DMA_STATUS_EB_MASK	dwmac_dma.h	/^#define DMA_STATUS_EB_MASK	/;"	d
DMA_STATUS_EB_RX_ABORT	dwmac_dma.h	/^#define DMA_STATUS_EB_RX_ABORT	/;"	d
DMA_STATUS_EB_TX_ABORT	dwmac_dma.h	/^#define DMA_STATUS_EB_TX_ABORT	/;"	d
DMA_STATUS_ERI	dwmac_dma.h	/^#define DMA_STATUS_ERI	/;"	d
DMA_STATUS_ETI	dwmac_dma.h	/^#define DMA_STATUS_ETI	/;"	d
DMA_STATUS_FBI	dwmac_dma.h	/^#define DMA_STATUS_FBI	/;"	d
DMA_STATUS_GLI	dwmac_dma.h	/^#define DMA_STATUS_GLI	/;"	d
DMA_STATUS_GLPII	dwmac_dma.h	/^#define DMA_STATUS_GLPII	/;"	d
DMA_STATUS_GMI	dwmac_dma.h	/^#define DMA_STATUS_GMI	/;"	d
DMA_STATUS_GPI	dwmac_dma.h	/^#define DMA_STATUS_GPI	/;"	d
DMA_STATUS_MAC	dwmac4_dma.h	/^#define DMA_STATUS_MAC	/;"	d
DMA_STATUS_MTL	dwmac4_dma.h	/^#define DMA_STATUS_MTL	/;"	d
DMA_STATUS_NIS	dwmac_dma.h	/^#define DMA_STATUS_NIS	/;"	d
DMA_STATUS_OVF	dwmac_dma.h	/^#define DMA_STATUS_OVF	/;"	d
DMA_STATUS_RI	dwmac_dma.h	/^#define DMA_STATUS_RI	/;"	d
DMA_STATUS_RPS	dwmac_dma.h	/^#define DMA_STATUS_RPS	/;"	d
DMA_STATUS_RS_MASK	dwmac_dma.h	/^#define DMA_STATUS_RS_MASK	/;"	d
DMA_STATUS_RS_SHIFT	dwmac_dma.h	/^#define DMA_STATUS_RS_SHIFT	/;"	d
DMA_STATUS_RU	dwmac_dma.h	/^#define DMA_STATUS_RU	/;"	d
DMA_STATUS_RWT	dwmac_dma.h	/^#define DMA_STATUS_RWT	/;"	d
DMA_STATUS_TI	dwmac_dma.h	/^#define DMA_STATUS_TI	/;"	d
DMA_STATUS_TJT	dwmac_dma.h	/^#define DMA_STATUS_TJT	/;"	d
DMA_STATUS_TPS	dwmac_dma.h	/^#define DMA_STATUS_TPS	/;"	d
DMA_STATUS_TS_MASK	dwmac_dma.h	/^#define DMA_STATUS_TS_MASK	/;"	d
DMA_STATUS_TS_SHIFT	dwmac_dma.h	/^#define DMA_STATUS_TS_SHIFT	/;"	d
DMA_STATUS_TU	dwmac_dma.h	/^#define DMA_STATUS_TU	/;"	d
DMA_STATUS_UNF	dwmac_dma.h	/^#define DMA_STATUS_UNF	/;"	d
DMA_SYS_BUS_AAL	dwmac4_dma.h	/^#define DMA_SYS_BUS_AAL	/;"	d
DMA_SYS_BUS_EAME	dwmac4_dma.h	/^#define DMA_SYS_BUS_EAME	/;"	d
DMA_SYS_BUS_FB	dwmac4_dma.h	/^#define DMA_SYS_BUS_FB	/;"	d
DMA_SYS_BUS_MB	dwmac4_dma.h	/^#define DMA_SYS_BUS_MB	/;"	d
DMA_SYS_BUS_MODE	dwmac4_dma.h	/^#define DMA_SYS_BUS_MODE	/;"	d
DMA_TBS_CTRL	dwmac4_dma.h	/^#define DMA_TBS_CTRL	/;"	d
DMA_TBS_DEF_FTOS	dwmac4_dma.h	/^#define DMA_TBS_DEF_FTOS	/;"	d
DMA_TBS_FTOS	dwmac4_dma.h	/^#define DMA_TBS_FTOS	/;"	d
DMA_TBS_FTOV	dwmac4_dma.h	/^#define DMA_TBS_FTOV	/;"	d
DMA_TX_BASE_ADDR	dwmac_dma.h	/^#define DMA_TX_BASE_ADDR	/;"	d
DMA_XMT_POLL_DEMAND	dwmac_dma.h	/^#define DMA_XMT_POLL_DEMAND	/;"	d
DRV_MODULE_VERSION	stmmac.h	/^#define DRV_MODULE_VERSION	/;"	d
DWMAC_125MHZ	dwmac-sti.c	/^#define DWMAC_125MHZ	/;"	d	file:
DWMAC_25MHZ	dwmac-sti.c	/^#define DWMAC_25MHZ	/;"	d	file:
DWMAC_2_5MHZ	dwmac-sti.c	/^#define DWMAC_2_5MHZ	/;"	d	file:
DWMAC_50MHZ	dwmac-sti.c	/^#define DWMAC_50MHZ	/;"	d	file:
DWMAC_ANARION	Kconfig	/^config DWMAC_ANARION$/;"	c
DWMAC_AUTO_TX_SOURCE	dwmac-oxnas.c	/^#define DWMAC_AUTO_TX_SOURCE /;"	d	file:
DWMAC_CKEN_GTX	dwmac-oxnas.c	/^#define DWMAC_CKEN_GTX /;"	d	file:
DWMAC_CKEN_RXN_OUT	dwmac-oxnas.c	/^#define DWMAC_CKEN_RXN_OUT /;"	d	file:
DWMAC_CKEN_RX_IN	dwmac-oxnas.c	/^#define DWMAC_CKEN_RX_IN /;"	d	file:
DWMAC_CKEN_RX_OUT	dwmac-oxnas.c	/^#define DWMAC_CKEN_RX_OUT /;"	d	file:
DWMAC_CKEN_TXN_OUT	dwmac-oxnas.c	/^#define DWMAC_CKEN_TXN_OUT /;"	d	file:
DWMAC_CKEN_TX_IN	dwmac-oxnas.c	/^#define DWMAC_CKEN_TX_IN /;"	d	file:
DWMAC_CKEN_TX_OUT	dwmac-oxnas.c	/^#define DWMAC_CKEN_TX_OUT /;"	d	file:
DWMAC_CORE_3_40	common.h	/^#define	DWMAC_CORE_3_40	/;"	d
DWMAC_CORE_3_50	common.h	/^#define	DWMAC_CORE_3_50	/;"	d
DWMAC_CORE_4_00	common.h	/^#define	DWMAC_CORE_4_00	/;"	d
DWMAC_CORE_4_10	common.h	/^#define DWMAC_CORE_4_10	/;"	d
DWMAC_CORE_5_00	common.h	/^#define DWMAC_CORE_5_00	/;"	d
DWMAC_CORE_5_10	common.h	/^#define DWMAC_CORE_5_10	/;"	d
DWMAC_DWC_QOS_ETH	Kconfig	/^config DWMAC_DWC_QOS_ETH$/;"	c
DWMAC_GENERIC	Kconfig	/^config DWMAC_GENERIC$/;"	c
DWMAC_IMX8	Kconfig	/^config DWMAC_IMX8$/;"	c
DWMAC_INTEL	Kconfig	/^config DWMAC_INTEL$/;"	c
DWMAC_INTEL_PLAT	Kconfig	/^config DWMAC_INTEL_PLAT$/;"	c
DWMAC_IPQ806X	Kconfig	/^config DWMAC_IPQ806X$/;"	c
DWMAC_LOW_TX_SOURCE	dwmac-oxnas.c	/^#define DWMAC_LOW_TX_SOURCE /;"	d	file:
DWMAC_LPC18XX	Kconfig	/^config DWMAC_LPC18XX$/;"	c
DWMAC_MEDIATEK	Kconfig	/^config DWMAC_MEDIATEK$/;"	c
DWMAC_MESON	Kconfig	/^config DWMAC_MESON$/;"	c
DWMAC_OXNAS	Kconfig	/^config DWMAC_OXNAS$/;"	c
DWMAC_QCOM_ETHQOS	Kconfig	/^config DWMAC_QCOM_ETHQOS$/;"	c
DWMAC_RGMII	dwmac-oxnas.c	/^#define DWMAC_RGMII /;"	d	file:
DWMAC_ROCKCHIP	Kconfig	/^config DWMAC_ROCKCHIP$/;"	c
DWMAC_RXN_VARDELAY	dwmac-oxnas.c	/^#define DWMAC_RXN_VARDELAY(/;"	d	file:
DWMAC_RXN_VARDELAY_SHIFT	dwmac-oxnas.c	/^#define DWMAC_RXN_VARDELAY_SHIFT	/;"	d	file:
DWMAC_RX_SOURCE	dwmac-oxnas.c	/^#define DWMAC_RX_SOURCE /;"	d	file:
DWMAC_RX_VARDELAY	dwmac-oxnas.c	/^#define DWMAC_RX_VARDELAY(/;"	d	file:
DWMAC_RX_VARDELAY_SHIFT	dwmac-oxnas.c	/^#define DWMAC_RX_VARDELAY_SHIFT	/;"	d	file:
DWMAC_SIMPLE_MUX	dwmac-oxnas.c	/^#define DWMAC_SIMPLE_MUX /;"	d	file:
DWMAC_SOCFPGA	Kconfig	/^config DWMAC_SOCFPGA$/;"	c
DWMAC_STI	Kconfig	/^config DWMAC_STI$/;"	c
DWMAC_STM32	Kconfig	/^config DWMAC_STM32$/;"	c
DWMAC_SUN8I	Kconfig	/^config DWMAC_SUN8I$/;"	c
DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	dwmac-sun8i.c	/^#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	/;"	d	file:
DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	dwmac-sun8i.c	/^#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	/;"	d	file:
DWMAC_SUNXI	Kconfig	/^config DWMAC_SUNXI$/;"	c
DWMAC_TXN_VARDELAY	dwmac-oxnas.c	/^#define DWMAC_TXN_VARDELAY(/;"	d	file:
DWMAC_TXN_VARDELAY_SHIFT	dwmac-oxnas.c	/^#define DWMAC_TXN_VARDELAY_SHIFT	/;"	d	file:
DWMAC_TX_SOURCE	dwmac-oxnas.c	/^#define DWMAC_TX_SOURCE /;"	d	file:
DWMAC_TX_VARDELAY	dwmac-oxnas.c	/^#define DWMAC_TX_VARDELAY(/;"	d	file:
DWMAC_TX_VARDELAY_SHIFT	dwmac-oxnas.c	/^#define DWMAC_TX_VARDELAY_SHIFT	/;"	d	file:
DWXGMAC_CORE_2_10	common.h	/^#define DWXGMAC_CORE_2_10	/;"	d
DWXGMAC_ID	common.h	/^#define DWXGMAC_ID	/;"	d
DWXLGMAC_CORE_2_00	common.h	/^#define DWXLGMAC_CORE_2_00	/;"	d
DWXLGMAC_ID	common.h	/^#define DWXLGMAC_ID	/;"	d
ECEIE	dwmac5.h	/^#define ECEIE	/;"	d
EDPP	dwmac5.h	/^#define EDPP	/;"	d
EEST	dwmac5.h	/^#define EEST	/;"	d
EFPE	dwmac5.h	/^#define EFPE	/;"	d
EMAC_BASIC_CTL0	dwmac-sun8i.c	/^#define EMAC_BASIC_CTL0 /;"	d	file:
EMAC_BASIC_CTL1	dwmac-sun8i.c	/^#define EMAC_BASIC_CTL1 /;"	d	file:
EMAC_BURSTLEN_SHIFT	dwmac-sun8i.c	/^#define EMAC_BURSTLEN_SHIFT	/;"	d	file:
EMAC_DUPLEX_FULL	dwmac-sun8i.c	/^#define EMAC_DUPLEX_FULL	/;"	d	file:
EMAC_FRM_FLT_CTL	dwmac-sun8i.c	/^#define EMAC_FRM_FLT_CTL /;"	d	file:
EMAC_FRM_FLT_MULTICAST	dwmac-sun8i.c	/^#define EMAC_FRM_FLT_MULTICAST /;"	d	file:
EMAC_FRM_FLT_RXALL	dwmac-sun8i.c	/^#define EMAC_FRM_FLT_RXALL /;"	d	file:
EMAC_INT_EN	dwmac-sun8i.c	/^#define EMAC_INT_EN /;"	d	file:
EMAC_INT_STA	dwmac-sun8i.c	/^#define EMAC_INT_STA /;"	d	file:
EMAC_LOOPBACK	dwmac-sun8i.c	/^#define EMAC_LOOPBACK	/;"	d	file:
EMAC_MACADDR_HI	dwmac-sun8i.c	/^#define EMAC_MACADDR_HI(/;"	d	file:
EMAC_MACADDR_LO	dwmac-sun8i.c	/^#define EMAC_MACADDR_LO(/;"	d	file:
EMAC_MDIO_CMD	dwmac-sun8i.c	/^#define EMAC_MDIO_CMD /;"	d	file:
EMAC_MDIO_DATA	dwmac-sun8i.c	/^#define EMAC_MDIO_DATA /;"	d	file:
EMAC_RGMII_STA_INT	dwmac-sun8i.c	/^#define EMAC_RGMII_STA_INT /;"	d	file:
EMAC_RX_BUF_UA_INT	dwmac-sun8i.c	/^#define EMAC_RX_BUF_UA_INT /;"	d	file:
EMAC_RX_CTL0	dwmac-sun8i.c	/^#define EMAC_RX_CTL0 /;"	d	file:
EMAC_RX_CTL1	dwmac-sun8i.c	/^#define EMAC_RX_CTL1 /;"	d	file:
EMAC_RX_CUR_BUF	dwmac-sun8i.c	/^#define EMAC_RX_CUR_BUF /;"	d	file:
EMAC_RX_CUR_DESC	dwmac-sun8i.c	/^#define EMAC_RX_CUR_DESC /;"	d	file:
EMAC_RX_DESC_LIST	dwmac-sun8i.c	/^#define EMAC_RX_DESC_LIST /;"	d	file:
EMAC_RX_DMA_EN	dwmac-sun8i.c	/^#define EMAC_RX_DMA_EN /;"	d	file:
EMAC_RX_DMA_STA	dwmac-sun8i.c	/^#define EMAC_RX_DMA_STA /;"	d	file:
EMAC_RX_DMA_START	dwmac-sun8i.c	/^#define EMAC_RX_DMA_START /;"	d	file:
EMAC_RX_DMA_STOP_INT	dwmac-sun8i.c	/^#define EMAC_RX_DMA_STOP_INT /;"	d	file:
EMAC_RX_DO_CRC	dwmac-sun8i.c	/^#define EMAC_RX_DO_CRC /;"	d	file:
EMAC_RX_EARLY_INT	dwmac-sun8i.c	/^#define EMAC_RX_EARLY_INT /;"	d	file:
EMAC_RX_FLOW_CTL_EN	dwmac-sun8i.c	/^#define EMAC_RX_FLOW_CTL_EN /;"	d	file:
EMAC_RX_FRM_FLT	dwmac-sun8i.c	/^#define EMAC_RX_FRM_FLT /;"	d	file:
EMAC_RX_INT	dwmac-sun8i.c	/^#define EMAC_RX_INT /;"	d	file:
EMAC_RX_MD	dwmac-sun8i.c	/^#define EMAC_RX_MD /;"	d	file:
EMAC_RX_OVERFLOW_INT	dwmac-sun8i.c	/^#define EMAC_RX_OVERFLOW_INT /;"	d	file:
EMAC_RX_RECEIVER_EN	dwmac-sun8i.c	/^#define EMAC_RX_RECEIVER_EN /;"	d	file:
EMAC_RX_TH_128	dwmac-sun8i.c	/^#define EMAC_RX_TH_128	/;"	d	file:
EMAC_RX_TH_32	dwmac-sun8i.c	/^#define EMAC_RX_TH_32	/;"	d	file:
EMAC_RX_TH_64	dwmac-sun8i.c	/^#define EMAC_RX_TH_64	/;"	d	file:
EMAC_RX_TH_96	dwmac-sun8i.c	/^#define EMAC_RX_TH_96	/;"	d	file:
EMAC_RX_TH_MASK	dwmac-sun8i.c	/^#define EMAC_RX_TH_MASK	/;"	d	file:
EMAC_RX_TIMEOUT_INT	dwmac-sun8i.c	/^#define EMAC_RX_TIMEOUT_INT /;"	d	file:
EMAC_SPEED_10	dwmac-sun8i.c	/^#define EMAC_SPEED_10 /;"	d	file:
EMAC_SPEED_100	dwmac-sun8i.c	/^#define EMAC_SPEED_100 /;"	d	file:
EMAC_SPEED_1000	dwmac-sun8i.c	/^#define EMAC_SPEED_1000 /;"	d	file:
EMAC_SPLITTER_CTRL_REG	dwmac-socfpga.c	/^#define EMAC_SPLITTER_CTRL_REG	/;"	d	file:
EMAC_SPLITTER_CTRL_SPEED_10	dwmac-socfpga.c	/^#define EMAC_SPLITTER_CTRL_SPEED_10	/;"	d	file:
EMAC_SPLITTER_CTRL_SPEED_100	dwmac-socfpga.c	/^#define EMAC_SPLITTER_CTRL_SPEED_100	/;"	d	file:
EMAC_SPLITTER_CTRL_SPEED_1000	dwmac-socfpga.c	/^#define EMAC_SPLITTER_CTRL_SPEED_1000	/;"	d	file:
EMAC_SPLITTER_CTRL_SPEED_MASK	dwmac-socfpga.c	/^#define EMAC_SPLITTER_CTRL_SPEED_MASK	/;"	d	file:
EMAC_SYSTEM_LOW_POWER_DEBUG	dwmac-qcom-ethqos.c	/^#define EMAC_SYSTEM_LOW_POWER_DEBUG	/;"	d	file:
EMAC_TX_BUF_UA_INT	dwmac-sun8i.c	/^#define EMAC_TX_BUF_UA_INT /;"	d	file:
EMAC_TX_CTL0	dwmac-sun8i.c	/^#define EMAC_TX_CTL0 /;"	d	file:
EMAC_TX_CTL1	dwmac-sun8i.c	/^#define EMAC_TX_CTL1 /;"	d	file:
EMAC_TX_CUR_BUF	dwmac-sun8i.c	/^#define EMAC_TX_CUR_BUF /;"	d	file:
EMAC_TX_CUR_DESC	dwmac-sun8i.c	/^#define EMAC_TX_CUR_DESC /;"	d	file:
EMAC_TX_DESC_LIST	dwmac-sun8i.c	/^#define EMAC_TX_DESC_LIST /;"	d	file:
EMAC_TX_DMA_EN	dwmac-sun8i.c	/^#define EMAC_TX_DMA_EN /;"	d	file:
EMAC_TX_DMA_STA	dwmac-sun8i.c	/^#define EMAC_TX_DMA_STA /;"	d	file:
EMAC_TX_DMA_START	dwmac-sun8i.c	/^#define EMAC_TX_DMA_START /;"	d	file:
EMAC_TX_DMA_STOP_INT	dwmac-sun8i.c	/^#define EMAC_TX_DMA_STOP_INT /;"	d	file:
EMAC_TX_EARLY_INT	dwmac-sun8i.c	/^#define EMAC_TX_EARLY_INT /;"	d	file:
EMAC_TX_FLOW_CTL	dwmac-sun8i.c	/^#define EMAC_TX_FLOW_CTL /;"	d	file:
EMAC_TX_FLOW_CTL_EN	dwmac-sun8i.c	/^#define EMAC_TX_FLOW_CTL_EN /;"	d	file:
EMAC_TX_INT	dwmac-sun8i.c	/^#define EMAC_TX_INT /;"	d	file:
EMAC_TX_MD	dwmac-sun8i.c	/^#define EMAC_TX_MD /;"	d	file:
EMAC_TX_NEXT_FRM	dwmac-sun8i.c	/^#define EMAC_TX_NEXT_FRM /;"	d	file:
EMAC_TX_TH_128	dwmac-sun8i.c	/^#define EMAC_TX_TH_128	/;"	d	file:
EMAC_TX_TH_192	dwmac-sun8i.c	/^#define EMAC_TX_TH_192	/;"	d	file:
EMAC_TX_TH_256	dwmac-sun8i.c	/^#define EMAC_TX_TH_256	/;"	d	file:
EMAC_TX_TH_64	dwmac-sun8i.c	/^#define EMAC_TX_TH_64	/;"	d	file:
EMAC_TX_TH_MASK	dwmac-sun8i.c	/^#define EMAC_TX_TH_MASK	/;"	d	file:
EMAC_TX_TIMEOUT_INT	dwmac-sun8i.c	/^#define EMAC_TX_TIMEOUT_INT /;"	d	file:
EMAC_TX_TRANSMITTER_EN	dwmac-sun8i.c	/^#define EMAC_TX_TRANSMITTER_EN /;"	d	file:
EMAC_TX_UNDERFLOW_INT	dwmac-sun8i.c	/^#define EMAC_TX_UNDERFLOW_INT /;"	d	file:
EN	dwmac-sti.c	/^#define EN	/;"	d	file:
ENMII	dwmac-sti.c	/^#define ENMII	/;"	d	file:
ENMII_MASK	dwmac-sti.c	/^#define ENMII_MASK	/;"	d	file:
EN_MASK	dwmac-sti.c	/^#define EN_MASK	/;"	d	file:
EPSI	dwmac5.h	/^#define EPSI	/;"	d
ERDES0_RX_MAC_ADDR	descs.h	/^#define	 ERDES0_RX_MAC_ADDR	/;"	d
ERDES1_BUFFER1_SIZE_MASK	descs.h	/^#define	ERDES1_BUFFER1_SIZE_MASK	/;"	d
ERDES1_BUFFER2_SIZE_MASK	descs.h	/^#define	ERDES1_BUFFER2_SIZE_MASK	/;"	d
ERDES1_BUFFER2_SIZE_SHIFT	descs.h	/^#define ERDES1_BUFFER2_SIZE_SHIFT	/;"	d
ERDES1_DISABLE_IC	descs.h	/^#define	ERDES1_DISABLE_IC	/;"	d
ERDES1_END_RING	descs.h	/^#define	ERDES1_END_RING	/;"	d
ERDES1_SECOND_ADDRESS_CHAINED	descs.h	/^#define	ERDES1_SECOND_ADDRESS_CHAINED	/;"	d
ERDES4_AV_PKT_RCVD	descs.h	/^#define	ERDES4_AV_PKT_RCVD	/;"	d
ERDES4_AV_TAGGED_PKT_RCVD	descs.h	/^#define	ERDES4_AV_TAGGED_PKT_RCVD	/;"	d
ERDES4_IPV4_PKT_RCVD	descs.h	/^#define	ERDES4_IPV4_PKT_RCVD	/;"	d
ERDES4_IPV6_PKT_RCVD	descs.h	/^#define	ERDES4_IPV6_PKT_RCVD	/;"	d
ERDES4_IP_CSUM_BYPASSED	descs.h	/^#define	ERDES4_IP_CSUM_BYPASSED	/;"	d
ERDES4_IP_HDR_ERR	descs.h	/^#define	ERDES4_IP_HDR_ERR	/;"	d
ERDES4_IP_PAYLOAD_ERR	descs.h	/^#define	ERDES4_IP_PAYLOAD_ERR	/;"	d
ERDES4_IP_PAYLOAD_TYPE_MASK	descs.h	/^#define	ERDES4_IP_PAYLOAD_TYPE_MASK	/;"	d
ERDES4_L3_FILTER_MATCH	descs.h	/^#define	ERDES4_L3_FILTER_MATCH	/;"	d
ERDES4_L3_L4_FILT_NO_MATCH_MASK	descs.h	/^#define	ERDES4_L3_L4_FILT_NO_MATCH_MASK	/;"	d
ERDES4_L4_FILTER_MATCH	descs.h	/^#define	ERDES4_L4_FILTER_MATCH	/;"	d
ERDES4_MSG_TYPE_MASK	descs.h	/^#define	ERDES4_MSG_TYPE_MASK	/;"	d
ERDES4_PTP_FRAME_TYPE	descs.h	/^#define	ERDES4_PTP_FRAME_TYPE	/;"	d
ERDES4_PTP_VER	descs.h	/^#define	ERDES4_PTP_VER	/;"	d
ERDES4_TIMESTAMP_DROPPED	descs.h	/^#define	ERDES4_TIMESTAMP_DROPPED	/;"	d
ERDES4_VLAN_TAG_PRI_VAL_MASK	descs.h	/^#define	ERDES4_VLAN_TAG_PRI_VAL_MASK	/;"	d
ETDES0_CHECKSUM_INSERTION_MASK	descs.h	/^#define	ETDES0_CHECKSUM_INSERTION_MASK	/;"	d
ETDES0_CHECKSUM_INSERTION_SHIFT	descs.h	/^#define	ETDES0_CHECKSUM_INSERTION_SHIFT	/;"	d
ETDES0_COLLISION_COUNT_MASK	descs.h	/^#define	ETDES0_COLLISION_COUNT_MASK	/;"	d
ETDES0_CRC_DISABLE	descs.h	/^#define	ETDES0_CRC_DISABLE	/;"	d
ETDES0_DEFERRED	descs.h	/^#define	ETDES0_DEFERRED	/;"	d
ETDES0_DISABLE_PADDING	descs.h	/^#define	ETDES0_DISABLE_PADDING	/;"	d
ETDES0_END_RING	descs.h	/^#define	ETDES0_END_RING	/;"	d
ETDES0_ERROR_SUMMARY	descs.h	/^#define	ETDES0_ERROR_SUMMARY	/;"	d
ETDES0_EXCESSIVE_COLLISIONS	descs.h	/^#define	ETDES0_EXCESSIVE_COLLISIONS	/;"	d
ETDES0_EXCESSIVE_DEFERRAL	descs.h	/^#define	ETDES0_EXCESSIVE_DEFERRAL	/;"	d
ETDES0_FIRST_SEGMENT	descs.h	/^#define	ETDES0_FIRST_SEGMENT	/;"	d
ETDES0_FRAME_FLUSHED	descs.h	/^#define	ETDES0_FRAME_FLUSHED	/;"	d
ETDES0_INTERRUPT	descs.h	/^#define	ETDES0_INTERRUPT	/;"	d
ETDES0_IP_HEADER_ERROR	descs.h	/^#define	ETDES0_IP_HEADER_ERROR	/;"	d
ETDES0_JABBER_TIMEOUT	descs.h	/^#define	ETDES0_JABBER_TIMEOUT	/;"	d
ETDES0_LAST_SEGMENT	descs.h	/^#define	ETDES0_LAST_SEGMENT	/;"	d
ETDES0_LATE_COLLISION	descs.h	/^#define	ETDES0_LATE_COLLISION	/;"	d
ETDES0_LOSS_CARRIER	descs.h	/^#define	ETDES0_LOSS_CARRIER	/;"	d
ETDES0_NO_CARRIER	descs.h	/^#define	ETDES0_NO_CARRIER	/;"	d
ETDES0_OWN	descs.h	/^#define	ETDES0_OWN	/;"	d
ETDES0_PAYLOAD_ERROR	descs.h	/^#define	ETDES0_PAYLOAD_ERROR	/;"	d
ETDES0_SECOND_ADDRESS_CHAINED	descs.h	/^#define	ETDES0_SECOND_ADDRESS_CHAINED	/;"	d
ETDES0_TIME_STAMP_ENABLE	descs.h	/^#define	ETDES0_TIME_STAMP_ENABLE	/;"	d
ETDES0_TIME_STAMP_STATUS	descs.h	/^#define	ETDES0_TIME_STAMP_STATUS	/;"	d
ETDES0_UNDERFLOW_ERROR	descs.h	/^#define	ETDES0_UNDERFLOW_ERROR	/;"	d
ETDES0_VLAN_FRAME	descs.h	/^#define	ETDES0_VLAN_FRAME	/;"	d
ETDES1_BUFFER1_SIZE_MASK	descs.h	/^#define	ETDES1_BUFFER1_SIZE_MASK	/;"	d
ETDES1_BUFFER2_SIZE_MASK	descs.h	/^#define	ETDES1_BUFFER2_SIZE_MASK	/;"	d
ETDES1_BUFFER2_SIZE_SHIFT	descs.h	/^#define	ETDES1_BUFFER2_SIZE_SHIFT	/;"	d
ETHMAC_SPEED_100	dwmac-meson.c	/^#define ETHMAC_SPEED_100	/;"	d	file:
ETHTOOL_DMA_OFFSET	stmmac_ethtool.c	/^#define ETHTOOL_DMA_OFFSET	/;"	d	file:
ETH_CK_F_125M	dwmac-stm32.c	/^#define ETH_CK_F_125M	/;"	d	file:
ETH_CK_F_25M	dwmac-stm32.c	/^#define ETH_CK_F_25M	/;"	d	file:
ETH_CK_F_50M	dwmac-stm32.c	/^#define ETH_CK_F_50M	/;"	d	file:
ETH_DLY_GTXC_ENABLE	dwmac-mediatek.c	/^#define ETH_DLY_GTXC_ENABLE	/;"	d	file:
ETH_DLY_GTXC_INV	dwmac-mediatek.c	/^#define ETH_DLY_GTXC_INV	/;"	d	file:
ETH_DLY_GTXC_STAGES	dwmac-mediatek.c	/^#define ETH_DLY_GTXC_STAGES	/;"	d	file:
ETH_DLY_RXC_ENABLE	dwmac-mediatek.c	/^#define ETH_DLY_RXC_ENABLE	/;"	d	file:
ETH_DLY_RXC_INV	dwmac-mediatek.c	/^#define ETH_DLY_RXC_INV	/;"	d	file:
ETH_DLY_RXC_STAGES	dwmac-mediatek.c	/^#define ETH_DLY_RXC_STAGES	/;"	d	file:
ETH_DLY_TXC_ENABLE	dwmac-mediatek.c	/^#define ETH_DLY_TXC_ENABLE	/;"	d	file:
ETH_DLY_TXC_INV	dwmac-mediatek.c	/^#define ETH_DLY_TXC_INV	/;"	d	file:
ETH_DLY_TXC_STAGES	dwmac-mediatek.c	/^#define ETH_DLY_TXC_STAGES	/;"	d	file:
ETH_FINE_DLY_GTXC	dwmac-mediatek.c	/^#define ETH_FINE_DLY_GTXC	/;"	d	file:
ETH_FINE_DLY_RXC	dwmac-mediatek.c	/^#define ETH_FINE_DLY_RXC	/;"	d	file:
ETH_PHY_SEL_GMII	dwmac-sti.c	/^#define ETH_PHY_SEL_GMII	/;"	d	file:
ETH_PHY_SEL_MII	dwmac-sti.c	/^#define ETH_PHY_SEL_MII	/;"	d	file:
ETH_PHY_SEL_RGMII	dwmac-sti.c	/^#define ETH_PHY_SEL_RGMII	/;"	d	file:
ETH_PHY_SEL_RMII	dwmac-sti.c	/^#define ETH_PHY_SEL_RMII	/;"	d	file:
ETH_PHY_SEL_SGMII	dwmac-sti.c	/^#define ETH_PHY_SEL_SGMII	/;"	d	file:
ETH_RMII_DLY_TX_INV	dwmac-mediatek.c	/^#define ETH_RMII_DLY_TX_INV	/;"	d	file:
FLOW_AUTO	common.h	/^#define FLOW_AUTO	/;"	d
FLOW_OFF	common.h	/^#define FLOW_OFF	/;"	d
FLOW_RX	common.h	/^#define FLOW_RX	/;"	d
FLOW_TX	common.h	/^#define FLOW_TX	/;"	d
GCRR	dwmac5.h	/^#define GCRR	/;"	d
GMAC4_LPI_CTRL_STATUS	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS	/;"	d
GMAC4_LPI_CTRL_STATUS_LPIEN	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_LPIEN	/;"	d
GMAC4_LPI_CTRL_STATUS_LPITCSE	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_LPITCSE	/;"	d
GMAC4_LPI_CTRL_STATUS_LPITXA	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_LPITXA	/;"	d
GMAC4_LPI_CTRL_STATUS_PLS	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_PLS	/;"	d
GMAC4_LPI_CTRL_STATUS_RLPIEN	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_RLPIEN	/;"	d
GMAC4_LPI_CTRL_STATUS_RLPIEX	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_RLPIEX	/;"	d
GMAC4_LPI_CTRL_STATUS_TLPIEN	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_TLPIEN	/;"	d
GMAC4_LPI_CTRL_STATUS_TLPIEX	dwmac4.h	/^#define GMAC4_LPI_CTRL_STATUS_TLPIEX	/;"	d
GMAC4_LPI_TIMER_CTRL	dwmac4.h	/^#define GMAC4_LPI_TIMER_CTRL	/;"	d
GMAC4_PTP_SSIR_SSINC_SHIFT	stmmac_ptp.h	/^#define	GMAC4_PTP_SSIR_SSINC_SHIFT	/;"	d
GMAC4_VERSION	hwif.h	/^#define GMAC4_VERSION	/;"	d
GMAC_1US_TIC_COUNTER	dwmac4.h	/^#define GMAC_1US_TIC_COUNTER	/;"	d
GMAC_ADDR_HIGH	dwmac1000.h	/^#define GMAC_ADDR_HIGH(/;"	d
GMAC_ADDR_HIGH	dwmac4.h	/^#define GMAC_ADDR_HIGH(/;"	d
GMAC_ADDR_LOW	dwmac1000.h	/^#define GMAC_ADDR_LOW(/;"	d
GMAC_ADDR_LOW	dwmac4.h	/^#define GMAC_ADDR_LOW(/;"	d
GMAC_ANE_ACK	stmmac_pcs.h	/^#define GMAC_ANE_ACK	/;"	d
GMAC_ANE_ADV	stmmac_pcs.h	/^#define GMAC_ANE_ADV(/;"	d
GMAC_ANE_EXP	stmmac_pcs.h	/^#define GMAC_ANE_EXP(/;"	d
GMAC_ANE_FD	stmmac_pcs.h	/^#define GMAC_ANE_FD	/;"	d
GMAC_ANE_HD	stmmac_pcs.h	/^#define GMAC_ANE_HD	/;"	d
GMAC_ANE_LPA	stmmac_pcs.h	/^#define GMAC_ANE_LPA(/;"	d
GMAC_ANE_PSE	stmmac_pcs.h	/^#define GMAC_ANE_PSE	/;"	d
GMAC_ANE_PSE_SHIFT	stmmac_pcs.h	/^#define GMAC_ANE_PSE_SHIFT	/;"	d
GMAC_ANE_RFE	stmmac_pcs.h	/^#define GMAC_ANE_RFE	/;"	d
GMAC_ANE_RFE_SHIFT	stmmac_pcs.h	/^#define GMAC_ANE_RFE_SHIFT	/;"	d
GMAC_AN_CTRL	stmmac_pcs.h	/^#define GMAC_AN_CTRL(/;"	d
GMAC_AN_CTRL_ANE	stmmac_pcs.h	/^#define GMAC_AN_CTRL_ANE	/;"	d
GMAC_AN_CTRL_ECD	stmmac_pcs.h	/^#define GMAC_AN_CTRL_ECD	/;"	d
GMAC_AN_CTRL_ELE	stmmac_pcs.h	/^#define GMAC_AN_CTRL_ELE	/;"	d
GMAC_AN_CTRL_LR	stmmac_pcs.h	/^#define GMAC_AN_CTRL_LR	/;"	d
GMAC_AN_CTRL_RAN	stmmac_pcs.h	/^#define GMAC_AN_CTRL_RAN	/;"	d
GMAC_AN_CTRL_SGMRAL	stmmac_pcs.h	/^#define GMAC_AN_CTRL_SGMRAL	/;"	d
GMAC_AN_STATUS	stmmac_pcs.h	/^#define GMAC_AN_STATUS(/;"	d
GMAC_AN_STATUS_ANA	stmmac_pcs.h	/^#define GMAC_AN_STATUS_ANA	/;"	d
GMAC_AN_STATUS_ANC	stmmac_pcs.h	/^#define GMAC_AN_STATUS_ANC	/;"	d
GMAC_AN_STATUS_ES	stmmac_pcs.h	/^#define GMAC_AN_STATUS_ES	/;"	d
GMAC_AN_STATUS_LS	stmmac_pcs.h	/^#define GMAC_AN_STATUS_LS	/;"	d
GMAC_ARP_ADDR	dwmac4.h	/^#define GMAC_ARP_ADDR	/;"	d
GMAC_CONFIG	dwmac4.h	/^#define GMAC_CONFIG	/;"	d
GMAC_CONFIG_2K	dwmac4.h	/^#define GMAC_CONFIG_2K	/;"	d
GMAC_CONFIG_ACS	dwmac4.h	/^#define GMAC_CONFIG_ACS	/;"	d
GMAC_CONFIG_ARPEN	dwmac4.h	/^#define GMAC_CONFIG_ARPEN	/;"	d
GMAC_CONFIG_BE	dwmac4.h	/^#define GMAC_CONFIG_BE	/;"	d
GMAC_CONFIG_DCRS	dwmac4.h	/^#define GMAC_CONFIG_DCRS	/;"	d
GMAC_CONFIG_DM	dwmac4.h	/^#define GMAC_CONFIG_DM	/;"	d
GMAC_CONFIG_EIPG	dwmac4.h	/^#define GMAC_CONFIG_EIPG	/;"	d
GMAC_CONFIG_EIPG_EN	dwmac4.h	/^#define GMAC_CONFIG_EIPG_EN	/;"	d
GMAC_CONFIG_EIPG_SHIFT	dwmac4.h	/^#define GMAC_CONFIG_EIPG_SHIFT	/;"	d
GMAC_CONFIG_FES	dwmac4.h	/^#define GMAC_CONFIG_FES	/;"	d
GMAC_CONFIG_FES_SHIFT	dwmac4.h	/^#define GMAC_CONFIG_FES_SHIFT	/;"	d
GMAC_CONFIG_HDSMS	dwmac4.h	/^#define GMAC_CONFIG_HDSMS	/;"	d
GMAC_CONFIG_HDSMS_256	dwmac4.h	/^#define GMAC_CONFIG_HDSMS_256	/;"	d
GMAC_CONFIG_HDSMS_SHIFT	dwmac4.h	/^#define GMAC_CONFIG_HDSMS_SHIFT	/;"	d
GMAC_CONFIG_INTF_RGMII	dwmac-anarion.c	/^#define  GMAC_CONFIG_INTF_RGMII	/;"	d	file:
GMAC_CONFIG_INTF_SEL_MASK	dwmac-anarion.c	/^#define  GMAC_CONFIG_INTF_SEL_MASK	/;"	d	file:
GMAC_CONFIG_IPC	dwmac4.h	/^#define GMAC_CONFIG_IPC	/;"	d
GMAC_CONFIG_IPG	dwmac4.h	/^#define GMAC_CONFIG_IPG	/;"	d
GMAC_CONFIG_IPG_SHIFT	dwmac4.h	/^#define GMAC_CONFIG_IPG_SHIFT	/;"	d
GMAC_CONFIG_JD	dwmac4.h	/^#define GMAC_CONFIG_JD	/;"	d
GMAC_CONFIG_JE	dwmac4.h	/^#define GMAC_CONFIG_JE	/;"	d
GMAC_CONFIG_LM	dwmac4.h	/^#define GMAC_CONFIG_LM	/;"	d
GMAC_CONFIG_PS	dwmac4.h	/^#define GMAC_CONFIG_PS	/;"	d
GMAC_CONFIG_RE	dwmac4.h	/^#define GMAC_CONFIG_RE	/;"	d
GMAC_CONFIG_SARC	dwmac4.h	/^#define GMAC_CONFIG_SARC	/;"	d
GMAC_CONFIG_SARC_SHIFT	dwmac4.h	/^#define GMAC_CONFIG_SARC_SHIFT	/;"	d
GMAC_CONFIG_TE	dwmac4.h	/^#define GMAC_CONFIG_TE	/;"	d
GMAC_CONTROL	dwmac1000.h	/^#define GMAC_CONTROL	/;"	d
GMAC_CONTROL_2K	dwmac1000.h	/^#define GMAC_CONTROL_2K /;"	d
GMAC_CONTROL_ACS	dwmac1000.h	/^#define GMAC_CONTROL_ACS	/;"	d
GMAC_CONTROL_BE	dwmac1000.h	/^#define GMAC_CONTROL_BE	/;"	d
GMAC_CONTROL_DC	dwmac1000.h	/^#define GMAC_CONTROL_DC	/;"	d
GMAC_CONTROL_DCRS	dwmac1000.h	/^#define GMAC_CONTROL_DCRS	/;"	d
GMAC_CONTROL_DM	dwmac1000.h	/^#define GMAC_CONTROL_DM	/;"	d
GMAC_CONTROL_DO	dwmac1000.h	/^#define GMAC_CONTROL_DO	/;"	d
GMAC_CONTROL_DR	dwmac1000.h	/^#define GMAC_CONTROL_DR	/;"	d
GMAC_CONTROL_FES	dwmac1000.h	/^#define GMAC_CONTROL_FES	/;"	d
GMAC_CONTROL_IFG_40	dwmac1000.h	/^	GMAC_CONTROL_IFG_40 = 0x000e0000,$/;"	e	enum:inter_frame_gap
GMAC_CONTROL_IFG_80	dwmac1000.h	/^	GMAC_CONTROL_IFG_80 = 0x00020000,$/;"	e	enum:inter_frame_gap
GMAC_CONTROL_IFG_88	dwmac1000.h	/^	GMAC_CONTROL_IFG_88 = 0x00040000,$/;"	e	enum:inter_frame_gap
GMAC_CONTROL_IPC	dwmac1000.h	/^#define GMAC_CONTROL_IPC	/;"	d
GMAC_CONTROL_JD	dwmac1000.h	/^#define GMAC_CONTROL_JD	/;"	d
GMAC_CONTROL_JE	dwmac1000.h	/^#define GMAC_CONTROL_JE	/;"	d
GMAC_CONTROL_LM	dwmac1000.h	/^#define GMAC_CONTROL_LM	/;"	d
GMAC_CONTROL_LUD	dwmac1000.h	/^#define GMAC_CONTROL_LUD	/;"	d
GMAC_CONTROL_PS	dwmac1000.h	/^#define GMAC_CONTROL_PS	/;"	d
GMAC_CONTROL_RE	dwmac1000.h	/^#define GMAC_CONTROL_RE	/;"	d
GMAC_CONTROL_TC	dwmac1000.h	/^#define GMAC_CONTROL_TC	/;"	d
GMAC_CONTROL_TE	dwmac1000.h	/^#define GMAC_CONTROL_TE	/;"	d
GMAC_CONTROL_WD	dwmac1000.h	/^#define GMAC_CONTROL_WD	/;"	d
GMAC_CORE_INIT	dwmac1000.h	/^#define GMAC_CORE_INIT /;"	d
GMAC_CORE_INIT	dwmac4.h	/^#define GMAC_CORE_INIT /;"	d
GMAC_DEBUG	dwmac1000.h	/^#define GMAC_DEBUG	/;"	d
GMAC_DEBUG	dwmac4.h	/^#define GMAC_DEBUG	/;"	d
GMAC_DEBUG_RFCFCSTS_MASK	dwmac1000.h	/^#define GMAC_DEBUG_RFCFCSTS_MASK	/;"	d
GMAC_DEBUG_RFCFCSTS_MASK	dwmac4.h	/^#define GMAC_DEBUG_RFCFCSTS_MASK	/;"	d
GMAC_DEBUG_RFCFCSTS_SHIFT	dwmac1000.h	/^#define GMAC_DEBUG_RFCFCSTS_SHIFT	/;"	d
GMAC_DEBUG_RFCFCSTS_SHIFT	dwmac4.h	/^#define GMAC_DEBUG_RFCFCSTS_SHIFT	/;"	d
GMAC_DEBUG_RPESTS	dwmac1000.h	/^#define GMAC_DEBUG_RPESTS	/;"	d
GMAC_DEBUG_RPESTS	dwmac4.h	/^#define GMAC_DEBUG_RPESTS	/;"	d
GMAC_DEBUG_RRCSTS_FLUSH	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_FLUSH	/;"	d
GMAC_DEBUG_RRCSTS_IDLE	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_IDLE	/;"	d
GMAC_DEBUG_RRCSTS_MASK	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_MASK	/;"	d
GMAC_DEBUG_RRCSTS_RDATA	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_RDATA	/;"	d
GMAC_DEBUG_RRCSTS_RSTAT	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_RSTAT	/;"	d
GMAC_DEBUG_RRCSTS_SHIFT	dwmac1000.h	/^#define GMAC_DEBUG_RRCSTS_SHIFT	/;"	d
GMAC_DEBUG_RWCSTS	dwmac1000.h	/^#define GMAC_DEBUG_RWCSTS	/;"	d
GMAC_DEBUG_RXFSTS_AT	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_AT	/;"	d
GMAC_DEBUG_RXFSTS_BT	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_BT	/;"	d
GMAC_DEBUG_RXFSTS_EMPTY	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_EMPTY	/;"	d
GMAC_DEBUG_RXFSTS_FULL	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_FULL	/;"	d
GMAC_DEBUG_RXFSTS_MASK	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_MASK	/;"	d
GMAC_DEBUG_RXFSTS_SHIFT	dwmac1000.h	/^#define GMAC_DEBUG_RXFSTS_SHIFT	/;"	d
GMAC_DEBUG_TFCSTS_GEN_PAUSE	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_GEN_PAUSE	/;"	d
GMAC_DEBUG_TFCSTS_GEN_PAUSE	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_GEN_PAUSE	/;"	d
GMAC_DEBUG_TFCSTS_IDLE	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_IDLE	/;"	d
GMAC_DEBUG_TFCSTS_IDLE	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_IDLE	/;"	d
GMAC_DEBUG_TFCSTS_MASK	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_MASK	/;"	d
GMAC_DEBUG_TFCSTS_MASK	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_MASK	/;"	d
GMAC_DEBUG_TFCSTS_SHIFT	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_SHIFT	/;"	d
GMAC_DEBUG_TFCSTS_SHIFT	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_SHIFT	/;"	d
GMAC_DEBUG_TFCSTS_WAIT	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_WAIT	/;"	d
GMAC_DEBUG_TFCSTS_WAIT	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_WAIT	/;"	d
GMAC_DEBUG_TFCSTS_XFER	dwmac1000.h	/^#define GMAC_DEBUG_TFCSTS_XFER	/;"	d
GMAC_DEBUG_TFCSTS_XFER	dwmac4.h	/^#define GMAC_DEBUG_TFCSTS_XFER	/;"	d
GMAC_DEBUG_TPESTS	dwmac1000.h	/^#define GMAC_DEBUG_TPESTS	/;"	d
GMAC_DEBUG_TPESTS	dwmac4.h	/^#define GMAC_DEBUG_TPESTS	/;"	d
GMAC_DEBUG_TRCSTS_IDLE	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_IDLE	/;"	d
GMAC_DEBUG_TRCSTS_MASK	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_MASK	/;"	d
GMAC_DEBUG_TRCSTS_READ	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_READ	/;"	d
GMAC_DEBUG_TRCSTS_SHIFT	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_SHIFT	/;"	d
GMAC_DEBUG_TRCSTS_TXW	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_TXW	/;"	d
GMAC_DEBUG_TRCSTS_WRITE	dwmac1000.h	/^#define GMAC_DEBUG_TRCSTS_WRITE	/;"	d
GMAC_DEBUG_TWCSTS	dwmac1000.h	/^#define GMAC_DEBUG_TWCSTS	/;"	d
GMAC_DEBUG_TXFSTS	dwmac1000.h	/^#define GMAC_DEBUG_TXFSTS	/;"	d
GMAC_DEBUG_TXPAUSED	dwmac1000.h	/^#define GMAC_DEBUG_TXPAUSED	/;"	d
GMAC_DEBUG_TXSTSFSTS	dwmac1000.h	/^#define GMAC_DEBUG_TXSTSFSTS	/;"	d
GMAC_ETHTOOL_NAME	stmmac_ethtool.c	/^#define GMAC_ETHTOOL_NAME	/;"	d	file:
GMAC_EXTHASH_BASE	dwmac1000.h	/^#define GMAC_EXTHASH_BASE /;"	d
GMAC_EXT_CONFIG	dwmac4.h	/^#define GMAC_EXT_CONFIG	/;"	d
GMAC_FLOW_CTRL	dwmac1000.h	/^#define GMAC_FLOW_CTRL	/;"	d
GMAC_FLOW_CTRL_FCB_BPA	dwmac1000.h	/^#define GMAC_FLOW_CTRL_FCB_BPA	/;"	d
GMAC_FLOW_CTRL_PT_MASK	dwmac1000.h	/^#define GMAC_FLOW_CTRL_PT_MASK	/;"	d
GMAC_FLOW_CTRL_PT_SHIFT	dwmac1000.h	/^#define GMAC_FLOW_CTRL_PT_SHIFT	/;"	d
GMAC_FLOW_CTRL_RFE	dwmac1000.h	/^#define GMAC_FLOW_CTRL_RFE	/;"	d
GMAC_FLOW_CTRL_TFE	dwmac1000.h	/^#define GMAC_FLOW_CTRL_TFE	/;"	d
GMAC_FLOW_CTRL_UP	dwmac1000.h	/^#define GMAC_FLOW_CTRL_UP	/;"	d
GMAC_FRAME_FILTER	dwmac1000.h	/^#define GMAC_FRAME_FILTER	/;"	d
GMAC_FRAME_FILTER_DAIF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_DAIF	/;"	d
GMAC_FRAME_FILTER_DBF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_DBF	/;"	d
GMAC_FRAME_FILTER_HMC	dwmac1000.h	/^#define GMAC_FRAME_FILTER_HMC	/;"	d
GMAC_FRAME_FILTER_HPF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_HPF	/;"	d
GMAC_FRAME_FILTER_HUC	dwmac1000.h	/^#define GMAC_FRAME_FILTER_HUC	/;"	d
GMAC_FRAME_FILTER_PCF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_PCF	/;"	d
GMAC_FRAME_FILTER_PM	dwmac1000.h	/^#define GMAC_FRAME_FILTER_PM	/;"	d
GMAC_FRAME_FILTER_PR	dwmac1000.h	/^#define GMAC_FRAME_FILTER_PR	/;"	d
GMAC_FRAME_FILTER_RA	dwmac1000.h	/^#define GMAC_FRAME_FILTER_RA	/;"	d
GMAC_FRAME_FILTER_SAF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_SAF	/;"	d
GMAC_FRAME_FILTER_SAIF	dwmac1000.h	/^#define GMAC_FRAME_FILTER_SAIF	/;"	d
GMAC_HASH_HIGH	dwmac1000.h	/^#define GMAC_HASH_HIGH	/;"	d
GMAC_HASH_LOW	dwmac1000.h	/^#define GMAC_HASH_LOW	/;"	d
GMAC_HASH_TAB	dwmac4.h	/^#define GMAC_HASH_TAB(/;"	d
GMAC_HI_DCS	dwmac4.h	/^#define GMAC_HI_DCS	/;"	d
GMAC_HI_DCS_SHIFT	dwmac4.h	/^#define GMAC_HI_DCS_SHIFT	/;"	d
GMAC_HI_REG_AE	dwmac4.h	/^#define GMAC_HI_REG_AE	/;"	d
GMAC_HI_REG_AE	dwmac_lib.c	/^#define GMAC_HI_REG_AE	/;"	d	file:
GMAC_HW_ADDR64	dwmac4.h	/^#define GMAC_HW_ADDR64	/;"	d
GMAC_HW_FEATURE0	dwmac4.h	/^#define GMAC_HW_FEATURE0	/;"	d
GMAC_HW_FEATURE1	dwmac4.h	/^#define GMAC_HW_FEATURE1	/;"	d
GMAC_HW_FEATURE2	dwmac4.h	/^#define GMAC_HW_FEATURE2	/;"	d
GMAC_HW_FEATURE3	dwmac4.h	/^#define GMAC_HW_FEATURE3	/;"	d
GMAC_HW_FEAT_ADDMAC	dwmac4.h	/^#define GMAC_HW_FEAT_ADDMAC	/;"	d
GMAC_HW_FEAT_ARPOFFSEL	dwmac4.h	/^#define GMAC_HW_FEAT_ARPOFFSEL	/;"	d
GMAC_HW_FEAT_ASP	dwmac4.h	/^#define GMAC_HW_FEAT_ASP	/;"	d
GMAC_HW_FEAT_AVSEL	dwmac4.h	/^#define GMAC_HW_FEAT_AVSEL	/;"	d
GMAC_HW_FEAT_DVLAN	dwmac4.h	/^#define GMAC_HW_FEAT_DVLAN	/;"	d
GMAC_HW_FEAT_EEESEL	dwmac4.h	/^#define GMAC_HW_FEAT_EEESEL	/;"	d
GMAC_HW_FEAT_ESTDEP	dwmac4.h	/^#define GMAC_HW_FEAT_ESTDEP	/;"	d
GMAC_HW_FEAT_ESTSEL	dwmac4.h	/^#define GMAC_HW_FEAT_ESTSEL	/;"	d
GMAC_HW_FEAT_ESTWID	dwmac4.h	/^#define GMAC_HW_FEAT_ESTWID	/;"	d
GMAC_HW_FEAT_FPESEL	dwmac4.h	/^#define GMAC_HW_FEAT_FPESEL	/;"	d
GMAC_HW_FEAT_FRPBS	dwmac4.h	/^#define GMAC_HW_FEAT_FRPBS	/;"	d
GMAC_HW_FEAT_FRPES	dwmac4.h	/^#define GMAC_HW_FEAT_FRPES	/;"	d
GMAC_HW_FEAT_FRPSEL	dwmac4.h	/^#define GMAC_HW_FEAT_FRPSEL	/;"	d
GMAC_HW_FEAT_GMIISEL	dwmac4.h	/^#define GMAC_HW_FEAT_GMIISEL	/;"	d
GMAC_HW_FEAT_HDSEL	dwmac4.h	/^#define GMAC_HW_FEAT_HDSEL	/;"	d
GMAC_HW_FEAT_L3L4FNUM	dwmac4.h	/^#define GMAC_HW_FEAT_L3L4FNUM	/;"	d
GMAC_HW_FEAT_MGKSEL	dwmac4.h	/^#define GMAC_HW_FEAT_MGKSEL	/;"	d
GMAC_HW_FEAT_MIISEL	dwmac4.h	/^#define GMAC_HW_FEAT_MIISEL	/;"	d
GMAC_HW_FEAT_MMCSEL	dwmac4.h	/^#define GMAC_HW_FEAT_MMCSEL	/;"	d
GMAC_HW_FEAT_NRVF	dwmac4.h	/^#define GMAC_HW_FEAT_NRVF	/;"	d
GMAC_HW_FEAT_PCSSEL	dwmac4.h	/^#define GMAC_HW_FEAT_PCSSEL	/;"	d
GMAC_HW_FEAT_PPSOUTNUM	dwmac4.h	/^#define GMAC_HW_FEAT_PPSOUTNUM	/;"	d
GMAC_HW_FEAT_RWKSEL	dwmac4.h	/^#define GMAC_HW_FEAT_RWKSEL	/;"	d
GMAC_HW_FEAT_RXCHCNT	dwmac4.h	/^#define GMAC_HW_FEAT_RXCHCNT	/;"	d
GMAC_HW_FEAT_RXCOESEL	dwmac4.h	/^#define GMAC_HW_FEAT_RXCOESEL	/;"	d
GMAC_HW_FEAT_RXQCNT	dwmac4.h	/^#define GMAC_HW_FEAT_RXQCNT	/;"	d
GMAC_HW_FEAT_SAVLANINS	dwmac4.h	/^#define GMAC_HW_FEAT_SAVLANINS	/;"	d
GMAC_HW_FEAT_SMASEL	dwmac4.h	/^#define GMAC_HW_FEAT_SMASEL	/;"	d
GMAC_HW_FEAT_SPHEN	dwmac4.h	/^#define GMAC_HW_FEAT_SPHEN	/;"	d
GMAC_HW_FEAT_TBSSEL	dwmac4.h	/^#define GMAC_HW_FEAT_TBSSEL	/;"	d
GMAC_HW_FEAT_TSSEL	dwmac4.h	/^#define GMAC_HW_FEAT_TSSEL	/;"	d
GMAC_HW_FEAT_TXCHCNT	dwmac4.h	/^#define GMAC_HW_FEAT_TXCHCNT	/;"	d
GMAC_HW_FEAT_TXCOSEL	dwmac4.h	/^#define GMAC_HW_FEAT_TXCOSEL	/;"	d
GMAC_HW_FEAT_TXQCNT	dwmac4.h	/^#define GMAC_HW_FEAT_TXQCNT	/;"	d
GMAC_HW_FEAT_VLHASH	dwmac4.h	/^#define GMAC_HW_FEAT_VLHASH	/;"	d
GMAC_HW_HASH_TB_SZ	dwmac4.h	/^#define GMAC_HW_HASH_TB_SZ	/;"	d
GMAC_HW_RXFIFOSIZE	dwmac4.h	/^#define GMAC_HW_RXFIFOSIZE	/;"	d
GMAC_HW_TSOEN	dwmac4.h	/^#define GMAC_HW_TSOEN	/;"	d
GMAC_HW_TXFIFOSIZE	dwmac4.h	/^#define GMAC_HW_TXFIFOSIZE	/;"	d
GMAC_INT_DEFAULT_ENABLE	dwmac4.h	/^#define	GMAC_INT_DEFAULT_ENABLE	/;"	d
GMAC_INT_DEFAULT_MASK	dwmac1000.h	/^#define	GMAC_INT_DEFAULT_MASK	/;"	d
GMAC_INT_DISABLE_PCS	dwmac1000.h	/^#define	GMAC_INT_DISABLE_PCS	/;"	d
GMAC_INT_DISABLE_PCSAN	dwmac1000.h	/^#define	GMAC_INT_DISABLE_PCSAN	/;"	d
GMAC_INT_DISABLE_PCSLINK	dwmac1000.h	/^#define	GMAC_INT_DISABLE_PCSLINK	/;"	d
GMAC_INT_DISABLE_PMT	dwmac1000.h	/^#define	GMAC_INT_DISABLE_PMT	/;"	d
GMAC_INT_DISABLE_RGMII	dwmac1000.h	/^#define	GMAC_INT_DISABLE_RGMII	/;"	d
GMAC_INT_DISABLE_TIMESTAMP	dwmac1000.h	/^#define	GMAC_INT_DISABLE_TIMESTAMP	/;"	d
GMAC_INT_EN	dwmac4.h	/^#define GMAC_INT_EN	/;"	d
GMAC_INT_LPI_EN	dwmac4.h	/^#define GMAC_INT_LPI_EN	/;"	d
GMAC_INT_MASK	dwmac1000.h	/^#define	GMAC_INT_MASK	/;"	d
GMAC_INT_PCS_ANE	dwmac4.h	/^#define GMAC_INT_PCS_ANE	/;"	d
GMAC_INT_PCS_LINK	dwmac4.h	/^#define GMAC_INT_PCS_LINK	/;"	d
GMAC_INT_PCS_PHYIS	dwmac4.h	/^#define GMAC_INT_PCS_PHYIS	/;"	d
GMAC_INT_PMT_EN	dwmac4.h	/^#define GMAC_INT_PMT_EN	/;"	d
GMAC_INT_RGSMIIS	dwmac4.h	/^#define GMAC_INT_RGSMIIS	/;"	d
GMAC_INT_STATUS	dwmac1000.h	/^#define GMAC_INT_STATUS	/;"	d
GMAC_INT_STATUS	dwmac4.h	/^#define GMAC_INT_STATUS	/;"	d
GMAC_INT_STATUS_LPIIS	dwmac1000.h	/^#define GMAC_INT_STATUS_LPIIS	/;"	d
GMAC_INT_STATUS_MMCCSUM	dwmac1000.h	/^#define GMAC_INT_STATUS_MMCCSUM	/;"	d
GMAC_INT_STATUS_MMCIS	dwmac1000.h	/^#define GMAC_INT_STATUS_MMCIS	/;"	d
GMAC_INT_STATUS_MMCRIS	dwmac1000.h	/^#define GMAC_INT_STATUS_MMCRIS	/;"	d
GMAC_INT_STATUS_MMCTIS	dwmac1000.h	/^#define GMAC_INT_STATUS_MMCTIS	/;"	d
GMAC_INT_STATUS_PMT	dwmac1000.h	/^#define GMAC_INT_STATUS_PMT	/;"	d
GMAC_INT_STATUS_TSTAMP	dwmac1000.h	/^#define GMAC_INT_STATUS_TSTAMP	/;"	d
GMAC_L3DAIM0	dwmac4.h	/^#define GMAC_L3DAIM0	/;"	d
GMAC_L3DAM0	dwmac4.h	/^#define GMAC_L3DAM0	/;"	d
GMAC_L3L4_CTRL	dwmac4.h	/^#define GMAC_L3L4_CTRL(/;"	d
GMAC_L3PEN0	dwmac4.h	/^#define GMAC_L3PEN0	/;"	d
GMAC_L3SAIM0	dwmac4.h	/^#define GMAC_L3SAIM0	/;"	d
GMAC_L3SAM0	dwmac4.h	/^#define GMAC_L3SAM0	/;"	d
GMAC_L3_ADDR0	dwmac4.h	/^#define GMAC_L3_ADDR0(/;"	d
GMAC_L3_ADDR1	dwmac4.h	/^#define GMAC_L3_ADDR1(/;"	d
GMAC_L4DP0	dwmac4.h	/^#define GMAC_L4DP0	/;"	d
GMAC_L4DP0_SHIFT	dwmac4.h	/^#define GMAC_L4DP0_SHIFT	/;"	d
GMAC_L4DPIM0	dwmac4.h	/^#define GMAC_L4DPIM0	/;"	d
GMAC_L4DPM0	dwmac4.h	/^#define GMAC_L4DPM0	/;"	d
GMAC_L4PEN0	dwmac4.h	/^#define GMAC_L4PEN0	/;"	d
GMAC_L4SP0	dwmac4.h	/^#define GMAC_L4SP0	/;"	d
GMAC_L4SPIM0	dwmac4.h	/^#define GMAC_L4SPIM0	/;"	d
GMAC_L4SPM0	dwmac4.h	/^#define GMAC_L4SPM0	/;"	d
GMAC_L4_ADDR	dwmac4.h	/^#define GMAC_L4_ADDR(/;"	d
GMAC_MAX_PERFECT_ADDRESSES	dwmac1000.h	/^#define GMAC_MAX_PERFECT_ADDRESSES	/;"	d
GMAC_MAX_PERFECT_ADDRESSES	dwmac4.h	/^#define GMAC_MAX_PERFECT_ADDRESSES	/;"	d
GMAC_MDIO_ADDR	dwmac4.h	/^#define GMAC_MDIO_ADDR	/;"	d
GMAC_MDIO_DATA	dwmac4.h	/^#define GMAC_MDIO_DATA	/;"	d
GMAC_MII_ADDR	dwmac1000.h	/^#define GMAC_MII_ADDR	/;"	d
GMAC_MII_ADDR_BUSY	dwmac1000.h	/^#define GMAC_MII_ADDR_BUSY	/;"	d
GMAC_MII_ADDR_WRITE	dwmac1000.h	/^#define GMAC_MII_ADDR_WRITE	/;"	d
GMAC_MII_DATA	dwmac1000.h	/^#define GMAC_MII_DATA	/;"	d
GMAC_MMC_CTRL	dwmac1000.h	/^#define GMAC_MMC_CTRL /;"	d
GMAC_MMC_RX_CSUM_OFFLOAD	dwmac1000.h	/^#define GMAC_MMC_RX_CSUM_OFFLOAD /;"	d
GMAC_MMC_RX_INTR	dwmac1000.h	/^#define GMAC_MMC_RX_INTR /;"	d
GMAC_MMC_TX_INTR	dwmac1000.h	/^#define GMAC_MMC_TX_INTR /;"	d
GMAC_PACKET_FILTER	dwmac4.h	/^#define GMAC_PACKET_FILTER	/;"	d
GMAC_PACKET_FILTER_HMC	dwmac4.h	/^#define GMAC_PACKET_FILTER_HMC	/;"	d
GMAC_PACKET_FILTER_HPF	dwmac4.h	/^#define GMAC_PACKET_FILTER_HPF	/;"	d
GMAC_PACKET_FILTER_IPFE	dwmac4.h	/^#define GMAC_PACKET_FILTER_IPFE	/;"	d
GMAC_PACKET_FILTER_PCF	dwmac4.h	/^#define GMAC_PACKET_FILTER_PCF	/;"	d
GMAC_PACKET_FILTER_PM	dwmac4.h	/^#define GMAC_PACKET_FILTER_PM	/;"	d
GMAC_PACKET_FILTER_PR	dwmac4.h	/^#define GMAC_PACKET_FILTER_PR	/;"	d
GMAC_PACKET_FILTER_RA	dwmac4.h	/^#define GMAC_PACKET_FILTER_RA	/;"	d
GMAC_PACKET_FILTER_VTFE	dwmac4.h	/^#define GMAC_PACKET_FILTER_VTFE	/;"	d
GMAC_PCS_BASE	dwmac1000.h	/^#define GMAC_PCS_BASE	/;"	d
GMAC_PCS_BASE	dwmac4.h	/^#define GMAC_PCS_BASE	/;"	d
GMAC_PCS_IRQ_DEFAULT	dwmac4.h	/^#define	GMAC_PCS_IRQ_DEFAULT	/;"	d
GMAC_PHYIF_CONTROL_STATUS	dwmac4.h	/^#define GMAC_PHYIF_CONTROL_STATUS	/;"	d
GMAC_PHYIF_CTRLSTATUS_FALSECARDET	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET	/;"	d
GMAC_PHYIF_CTRLSTATUS_JABTO	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_JABTO	/;"	d
GMAC_PHYIF_CTRLSTATUS_LNKMOD	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_LNKMOD	/;"	d
GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK	/;"	d
GMAC_PHYIF_CTRLSTATUS_LNKSTS	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_LNKSTS	/;"	d
GMAC_PHYIF_CTRLSTATUS_LUD	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_LUD	/;"	d
GMAC_PHYIF_CTRLSTATUS_SMIDRXS	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS	/;"	d
GMAC_PHYIF_CTRLSTATUS_SPEED	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SPEED	/;"	d
GMAC_PHYIF_CTRLSTATUS_SPEED_125	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SPEED_125	/;"	d
GMAC_PHYIF_CTRLSTATUS_SPEED_25	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SPEED_25	/;"	d
GMAC_PHYIF_CTRLSTATUS_SPEED_2_5	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5	/;"	d
GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	/;"	d
GMAC_PHYIF_CTRLSTATUS_TC	dwmac4.h	/^#define GMAC_PHYIF_CTRLSTATUS_TC	/;"	d
GMAC_PMT	dwmac1000.h	/^#define GMAC_PMT	/;"	d
GMAC_PMT	dwmac4.h	/^#define GMAC_PMT	/;"	d
GMAC_QX_TX_FLOW_CTRL	dwmac4.h	/^#define GMAC_QX_TX_FLOW_CTRL(/;"	d
GMAC_REG_NUM	dwmac4.h	/^#define	GMAC_REG_NUM	/;"	d
GMAC_RESET_CONTROL_REG	dwmac-anarion.c	/^#define GMAC_RESET_CONTROL_REG	/;"	d	file:
GMAC_RGSMIIIS	dwmac1000.h	/^#define GMAC_RGSMIIIS	/;"	d
GMAC_RGSMIIIS_FALSECARDET	dwmac1000.h	/^#define GMAC_RGSMIIIS_FALSECARDET	/;"	d
GMAC_RGSMIIIS_JABTO	dwmac1000.h	/^#define GMAC_RGSMIIIS_JABTO	/;"	d
GMAC_RGSMIIIS_LNKMODE	dwmac1000.h	/^#define GMAC_RGSMIIIS_LNKMODE	/;"	d
GMAC_RGSMIIIS_LNKMOD_MASK	dwmac1000.h	/^#define GMAC_RGSMIIIS_LNKMOD_MASK	/;"	d
GMAC_RGSMIIIS_LNKSTS	dwmac1000.h	/^#define GMAC_RGSMIIIS_LNKSTS	/;"	d
GMAC_RGSMIIIS_SMIDRXS	dwmac1000.h	/^#define GMAC_RGSMIIIS_SMIDRXS	/;"	d
GMAC_RGSMIIIS_SPEED	dwmac1000.h	/^#define GMAC_RGSMIIIS_SPEED	/;"	d
GMAC_RGSMIIIS_SPEED_125	dwmac1000.h	/^#define GMAC_RGSMIIIS_SPEED_125	/;"	d
GMAC_RGSMIIIS_SPEED_25	dwmac1000.h	/^#define GMAC_RGSMIIIS_SPEED_25	/;"	d
GMAC_RGSMIIIS_SPEED_2_5	dwmac1000.h	/^#define GMAC_RGSMIIIS_SPEED_2_5	/;"	d
GMAC_RGSMIIIS_SPEED_SHIFT	dwmac1000.h	/^#define GMAC_RGSMIIIS_SPEED_SHIFT	/;"	d
GMAC_RXQCTRL_AVCPQ_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_AVCPQ_MASK	/;"	d
GMAC_RXQCTRL_AVCPQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_AVCPQ_SHIFT	/;"	d
GMAC_RXQCTRL_DCBCPQ_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_DCBCPQ_MASK	/;"	d
GMAC_RXQCTRL_DCBCPQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_DCBCPQ_SHIFT	/;"	d
GMAC_RXQCTRL_FPRQ	dwmac4.h	/^#define GMAC_RXQCTRL_FPRQ	/;"	d
GMAC_RXQCTRL_FPRQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_FPRQ_SHIFT	/;"	d
GMAC_RXQCTRL_MCBCQEN	dwmac4.h	/^#define GMAC_RXQCTRL_MCBCQEN	/;"	d
GMAC_RXQCTRL_MCBCQEN_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_MCBCQEN_SHIFT	/;"	d
GMAC_RXQCTRL_MCBCQ_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_MCBCQ_MASK	/;"	d
GMAC_RXQCTRL_MCBCQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_MCBCQ_SHIFT	/;"	d
GMAC_RXQCTRL_PSRQX_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_PSRQX_MASK(/;"	d
GMAC_RXQCTRL_PSRQX_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_PSRQX_SHIFT(/;"	d
GMAC_RXQCTRL_PTPQ_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_PTPQ_MASK	/;"	d
GMAC_RXQCTRL_PTPQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_PTPQ_SHIFT	/;"	d
GMAC_RXQCTRL_TACPQE	dwmac4.h	/^#define GMAC_RXQCTRL_TACPQE	/;"	d
GMAC_RXQCTRL_TACPQE_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_TACPQE_SHIFT	/;"	d
GMAC_RXQCTRL_UPQ_MASK	dwmac4.h	/^#define GMAC_RXQCTRL_UPQ_MASK	/;"	d
GMAC_RXQCTRL_UPQ_SHIFT	dwmac4.h	/^#define GMAC_RXQCTRL_UPQ_SHIFT	/;"	d
GMAC_RXQCTRL_VFFQE	dwmac5.h	/^#define GMAC_RXQCTRL_VFFQE	/;"	d
GMAC_RXQCTRL_VFFQ_MASK	dwmac5.h	/^#define GMAC_RXQCTRL_VFFQ_MASK	/;"	d
GMAC_RXQCTRL_VFFQ_SHIFT	dwmac5.h	/^#define GMAC_RXQCTRL_VFFQ_SHIFT	/;"	d
GMAC_RXQ_CTRL0	dwmac4.h	/^#define GMAC_RXQ_CTRL0	/;"	d
GMAC_RXQ_CTRL1	dwmac4.h	/^#define GMAC_RXQ_CTRL1	/;"	d
GMAC_RXQ_CTRL2	dwmac4.h	/^#define GMAC_RXQ_CTRL2	/;"	d
GMAC_RXQ_CTRL3	dwmac4.h	/^#define GMAC_RXQ_CTRL3	/;"	d
GMAC_RXQ_CTRL4	dwmac5.h	/^#define GMAC_RXQ_CTRL4	/;"	d
GMAC_RX_AV_QUEUE_ENABLE	dwmac4.h	/^#define GMAC_RX_AV_QUEUE_ENABLE(/;"	d
GMAC_RX_DCB_QUEUE_ENABLE	dwmac4.h	/^#define GMAC_RX_DCB_QUEUE_ENABLE(/;"	d
GMAC_RX_FLOW_CTRL	dwmac4.h	/^#define GMAC_RX_FLOW_CTRL	/;"	d
GMAC_RX_FLOW_CTRL_RFE	dwmac4.h	/^#define GMAC_RX_FLOW_CTRL_RFE	/;"	d
GMAC_RX_QUEUE_CLEAR	dwmac4.h	/^#define GMAC_RX_QUEUE_CLEAR(/;"	d
GMAC_SW_CONFIG_REG	dwmac-anarion.c	/^#define GMAC_SW_CONFIG_REG	/;"	d	file:
GMAC_TBI	stmmac_pcs.h	/^#define GMAC_TBI(/;"	d
GMAC_TXQCTRL_PSTQX_MASK	dwmac4.h	/^#define GMAC_TXQCTRL_PSTQX_MASK(/;"	d
GMAC_TXQCTRL_PSTQX_SHIFT	dwmac4.h	/^#define GMAC_TXQCTRL_PSTQX_SHIFT(/;"	d
GMAC_TXQ_PRTY_MAP0	dwmac4.h	/^#define GMAC_TXQ_PRTY_MAP0	/;"	d
GMAC_TXQ_PRTY_MAP1	dwmac4.h	/^#define GMAC_TXQ_PRTY_MAP1	/;"	d
GMAC_TX_FLOW_CTRL_PT_SHIFT	dwmac4.h	/^#define GMAC_TX_FLOW_CTRL_PT_SHIFT	/;"	d
GMAC_TX_FLOW_CTRL_TFE	dwmac4.h	/^#define GMAC_TX_FLOW_CTRL_TFE	/;"	d
GMAC_VERSION	hwif.h	/^#define GMAC_VERSION	/;"	d
GMAC_VLAN_CSVL	dwmac4.h	/^#define GMAC_VLAN_CSVL	/;"	d
GMAC_VLAN_DOVLTC	dwmac4.h	/^#define GMAC_VLAN_DOVLTC	/;"	d
GMAC_VLAN_EDVLP	dwmac4.h	/^#define GMAC_VLAN_EDVLP	/;"	d
GMAC_VLAN_ESVL	dwmac4.h	/^#define GMAC_VLAN_ESVL	/;"	d
GMAC_VLAN_ETV	dwmac4.h	/^#define GMAC_VLAN_ETV	/;"	d
GMAC_VLAN_HASH_TABLE	dwmac4.h	/^#define GMAC_VLAN_HASH_TABLE	/;"	d
GMAC_VLAN_INCL	dwmac4.h	/^#define GMAC_VLAN_INCL	/;"	d
GMAC_VLAN_TAG	dwmac1000.h	/^#define GMAC_VLAN_TAG	/;"	d
GMAC_VLAN_TAG	dwmac4.h	/^#define GMAC_VLAN_TAG	/;"	d
GMAC_VLAN_TAG_CTRL_CT	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_CT	/;"	d
GMAC_VLAN_TAG_CTRL_EVLRXS	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_EVLRXS	/;"	d
GMAC_VLAN_TAG_CTRL_EVLS_MASK	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_EVLS_MASK	/;"	d
GMAC_VLAN_TAG_CTRL_EVLS_SHIFT	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT	/;"	d
GMAC_VLAN_TAG_CTRL_OB	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_OB	/;"	d
GMAC_VLAN_TAG_CTRL_OFS_MASK	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_OFS_MASK	/;"	d
GMAC_VLAN_TAG_CTRL_OFS_SHIFT	dwmac4.h	/^#define GMAC_VLAN_TAG_CTRL_OFS_SHIFT	/;"	d
GMAC_VLAN_TAG_DATA	dwmac4.h	/^#define GMAC_VLAN_TAG_DATA	/;"	d
GMAC_VLAN_TAG_DATA_ETV	dwmac4.h	/^#define GMAC_VLAN_TAG_DATA_ETV	/;"	d
GMAC_VLAN_TAG_DATA_VEN	dwmac4.h	/^#define GMAC_VLAN_TAG_DATA_VEN	/;"	d
GMAC_VLAN_TAG_DATA_VID	dwmac4.h	/^#define GMAC_VLAN_TAG_DATA_VID	/;"	d
GMAC_VLAN_TAG_ETV	dwmac4.h	/^#define GMAC_VLAN_TAG_ETV	/;"	d
GMAC_VLAN_TAG_STRIP_ALL	dwmac4.h	/^#define GMAC_VLAN_TAG_STRIP_ALL	/;"	d
GMAC_VLAN_TAG_STRIP_FAIL	dwmac4.h	/^#define GMAC_VLAN_TAG_STRIP_FAIL	/;"	d
GMAC_VLAN_TAG_STRIP_NONE	dwmac4.h	/^#define GMAC_VLAN_TAG_STRIP_NONE	/;"	d
GMAC_VLAN_TAG_STRIP_PASS	dwmac4.h	/^#define GMAC_VLAN_TAG_STRIP_PASS	/;"	d
GMAC_VLAN_TAG_VID	dwmac4.h	/^#define GMAC_VLAN_TAG_VID	/;"	d
GMAC_VLAN_VID	dwmac4.h	/^#define GMAC_VLAN_VID	/;"	d
GMAC_VLAN_VLC	dwmac4.h	/^#define GMAC_VLAN_VLC	/;"	d
GMAC_VLAN_VLC_SHIFT	dwmac4.h	/^#define GMAC_VLAN_VLC_SHIFT	/;"	d
GMAC_VLAN_VLHT	dwmac4.h	/^#define GMAC_VLAN_VLHT	/;"	d
GMAC_VLAN_VLTI	dwmac4.h	/^#define GMAC_VLAN_VLTI	/;"	d
GMAC_VLAN_VTHM	dwmac4.h	/^#define GMAC_VLAN_VTHM	/;"	d
GMAC_WAKEUP_FILTER	dwmac1000.h	/^#define GMAC_WAKEUP_FILTER	/;"	d
GPR_ENET_QOS_CLK_GEN_EN	dwmac-imx.c	/^#define GPR_ENET_QOS_CLK_GEN_EN	/;"	d	file:
GPR_ENET_QOS_CLK_TX_CLK_SEL	dwmac-imx.c	/^#define GPR_ENET_QOS_CLK_TX_CLK_SEL	/;"	d	file:
GPR_ENET_QOS_INTF_MODE_MASK	dwmac-imx.c	/^#define GPR_ENET_QOS_INTF_MODE_MASK	/;"	d	file:
GPR_ENET_QOS_INTF_SEL_MII	dwmac-imx.c	/^#define GPR_ENET_QOS_INTF_SEL_MII	/;"	d	file:
GPR_ENET_QOS_INTF_SEL_RGMII	dwmac-imx.c	/^#define GPR_ENET_QOS_INTF_SEL_RGMII	/;"	d	file:
GPR_ENET_QOS_INTF_SEL_RMII	dwmac-imx.c	/^#define GPR_ENET_QOS_INTF_SEL_RMII	/;"	d	file:
GPR_ENET_QOS_RGMII_EN	dwmac-imx.c	/^#define GPR_ENET_QOS_RGMII_EN	/;"	d	file:
GRF_BIT	dwmac-rk.c	/^#define GRF_BIT(/;"	d	file:
GRF_CLR_BIT	dwmac-rk.c	/^#define GRF_CLR_BIT(/;"	d	file:
H3_EPHY_ADDR_SHIFT	dwmac-sun8i.c	/^#define H3_EPHY_ADDR_SHIFT	/;"	d	file:
H3_EPHY_CLK_SEL	dwmac-sun8i.c	/^#define H3_EPHY_CLK_SEL	/;"	d	file:
H3_EPHY_LED_POL	dwmac-sun8i.c	/^#define H3_EPHY_LED_POL	/;"	d	file:
H3_EPHY_MUX_MASK	dwmac-sun8i.c	/^#define H3_EPHY_MUX_MASK	/;"	d	file:
H3_EPHY_SELECT	dwmac-sun8i.c	/^#define H3_EPHY_SELECT	/;"	d	file:
H3_EPHY_SHUTDOWN	dwmac-sun8i.c	/^#define H3_EPHY_SHUTDOWN	/;"	d	file:
HASH_TABLE_SIZE	common.h	/^#define HASH_TABLE_SIZE /;"	d
HIWORD_UPDATE	dwmac-rk.c	/^#define HIWORD_UPDATE(/;"	d	file:
IS_PHY_IF_MODE_GBIT	dwmac-sti.c	/^#define IS_PHY_IF_MODE_GBIT(/;"	d	file:
IS_PHY_IF_MODE_RGMII	dwmac-sti.c	/^#define IS_PHY_IF_MODE_RGMII(/;"	d	file:
JUMBO_LEN	common.h	/^#define JUMBO_LEN	/;"	d
LLR	dwmac5.h	/^#define LLR	/;"	d
LPC18XX_CREG_CREG6	dwmac-lpc18xx.c	/^#define LPC18XX_CREG_CREG6	/;"	d	file:
LPC18XX_CREG_CREG6_ETHMODE_MASK	dwmac-lpc18xx.c	/^# define LPC18XX_CREG_CREG6_ETHMODE_MASK	/;"	d	file:
LPC18XX_CREG_CREG6_ETHMODE_MII	dwmac-lpc18xx.c	/^# define LPC18XX_CREG_CREG6_ETHMODE_MII	/;"	d	file:
LPC18XX_CREG_CREG6_ETHMODE_RMII	dwmac-lpc18xx.c	/^# define LPC18XX_CREG_CREG6_ETHMODE_RMII	/;"	d	file:
LPI_CTRL_STATUS	dwmac1000.h	/^#define LPI_CTRL_STATUS	/;"	d
LPI_CTRL_STATUS_LPIEN	dwmac1000.h	/^#define LPI_CTRL_STATUS_LPIEN	/;"	d
LPI_CTRL_STATUS_LPITXA	dwmac1000.h	/^#define LPI_CTRL_STATUS_LPITXA	/;"	d
LPI_CTRL_STATUS_PLS	dwmac1000.h	/^#define LPI_CTRL_STATUS_PLS	/;"	d
LPI_CTRL_STATUS_PLSEN	dwmac1000.h	/^#define LPI_CTRL_STATUS_PLSEN	/;"	d
LPI_CTRL_STATUS_RLPIEN	dwmac1000.h	/^#define LPI_CTRL_STATUS_RLPIEN	/;"	d
LPI_CTRL_STATUS_RLPIEX	dwmac1000.h	/^#define LPI_CTRL_STATUS_RLPIEX	/;"	d
LPI_CTRL_STATUS_RLPIST	dwmac1000.h	/^#define LPI_CTRL_STATUS_RLPIST	/;"	d
LPI_CTRL_STATUS_TLPIEN	dwmac1000.h	/^#define LPI_CTRL_STATUS_TLPIEN	/;"	d
LPI_CTRL_STATUS_TLPIEX	dwmac1000.h	/^#define LPI_CTRL_STATUS_TLPIEX	/;"	d
LPI_CTRL_STATUS_TLPIST	dwmac1000.h	/^#define LPI_CTRL_STATUS_TLPIST	/;"	d
LPI_TIMER_CTRL	dwmac1000.h	/^#define LPI_TIMER_CTRL	/;"	d
M	dkms.conf	/^MAKE[0]="make -C ${kernel_source_dir} M=${dkms_tree}\/${PACKAGE_NAME}\/${PACKAGE_VERSION}\/build/;"	k
MAC100_ETHTOOL_NAME	stmmac_ethtool.c	/^#define MAC100_ETHTOOL_NAME	/;"	d	file:
MAC_ADDR_HIGH	dwmac100.h	/^#define MAC_ADDR_HIGH	/;"	d
MAC_ADDR_LOW	dwmac100.h	/^#define MAC_ADDR_LOW	/;"	d
MAC_ADDR_TYPE_DST	dwmac-sun8i.c	/^#define MAC_ADDR_TYPE_DST /;"	d	file:
MAC_AXI_SLV_DPE_ADDR_STATUS	dwmac5.h	/^#define MAC_AXI_SLV_DPE_ADDR_STATUS	/;"	d
MAC_CONTROL	dwmac100.h	/^#define MAC_CONTROL	/;"	d
MAC_CONTROL_ASTP	dwmac100.h	/^#define MAC_CONTROL_ASTP	/;"	d
MAC_CONTROL_BLE	dwmac100.h	/^#define MAC_CONTROL_BLE	/;"	d
MAC_CONTROL_BOLMT_1	dwmac100.h	/^#define MAC_CONTROL_BOLMT_1	/;"	d
MAC_CONTROL_BOLMT_10	dwmac100.h	/^#define MAC_CONTROL_BOLMT_10	/;"	d
MAC_CONTROL_BOLMT_4	dwmac100.h	/^#define MAC_CONTROL_BOLMT_4	/;"	d
MAC_CONTROL_BOLMT_8	dwmac100.h	/^#define MAC_CONTROL_BOLMT_8	/;"	d
MAC_CONTROL_DBF	dwmac100.h	/^#define MAC_CONTROL_DBF	/;"	d
MAC_CONTROL_DC	dwmac100.h	/^#define MAC_CONTROL_DC	/;"	d
MAC_CONTROL_DRO	dwmac100.h	/^#define MAC_CONTROL_DRO	/;"	d
MAC_CONTROL_DRTY	dwmac100.h	/^#define MAC_CONTROL_DRTY	/;"	d
MAC_CONTROL_EXT_LOOPBACK	dwmac100.h	/^#define MAC_CONTROL_EXT_LOOPBACK /;"	d
MAC_CONTROL_F	dwmac100.h	/^#define MAC_CONTROL_F	/;"	d
MAC_CONTROL_HBD	dwmac100.h	/^#define MAC_CONTROL_HBD	/;"	d
MAC_CONTROL_HO	dwmac100.h	/^#define MAC_CONTROL_HO	/;"	d
MAC_CONTROL_HP	dwmac100.h	/^#define MAC_CONTROL_HP	/;"	d
MAC_CONTROL_IF	dwmac100.h	/^#define MAC_CONTROL_IF	/;"	d
MAC_CONTROL_LCC	dwmac100.h	/^#define MAC_CONTROL_LCC	/;"	d
MAC_CONTROL_OM	dwmac100.h	/^#define MAC_CONTROL_OM	/;"	d
MAC_CONTROL_PB	dwmac100.h	/^#define MAC_CONTROL_PB	/;"	d
MAC_CONTROL_PM	dwmac100.h	/^#define MAC_CONTROL_PM	/;"	d
MAC_CONTROL_PR	dwmac100.h	/^#define MAC_CONTROL_PR	/;"	d
MAC_CONTROL_PS	dwmac100.h	/^#define MAC_CONTROL_PS	/;"	d
MAC_CONTROL_RA	dwmac100.h	/^#define MAC_CONTROL_RA	/;"	d
MAC_CONTROL_RE	dwmac100.h	/^#define MAC_CONTROL_RE	/;"	d
MAC_CONTROL_TE	dwmac100.h	/^#define MAC_CONTROL_TE	/;"	d
MAC_CORE_INIT	dwmac100.h	/^#define MAC_CORE_INIT /;"	d
MAC_CSR_H_FRQ_MASK	common.h	/^#define	MAC_CSR_H_FRQ_MASK	/;"	d
MAC_CTRL_REG	common.h	/^#define MAC_CTRL_REG	/;"	d
MAC_DPP_FSM_INT_STATUS	dwmac5.h	/^#define MAC_DPP_FSM_INT_STATUS	/;"	d
MAC_ENABLE_RX	common.h	/^#define MAC_ENABLE_RX	/;"	d
MAC_ENABLE_TX	common.h	/^#define MAC_ENABLE_TX	/;"	d
MAC_FLOW_CTRL	dwmac100.h	/^#define MAC_FLOW_CTRL	/;"	d
MAC_FLOW_CTRL_ENABLE	dwmac100.h	/^#define MAC_FLOW_CTRL_ENABLE	/;"	d
MAC_FLOW_CTRL_PASS	dwmac100.h	/^#define MAC_FLOW_CTRL_PASS	/;"	d
MAC_FLOW_CTRL_PAUSE	dwmac100.h	/^#define MAC_FLOW_CTRL_PAUSE	/;"	d
MAC_FLOW_CTRL_PT_MASK	dwmac100.h	/^#define MAC_FLOW_CTRL_PT_MASK	/;"	d
MAC_FLOW_CTRL_PT_SHIFT	dwmac100.h	/^#define MAC_FLOW_CTRL_PT_SHIFT	/;"	d
MAC_FPE_CTRL_STS	dwmac5.h	/^#define MAC_FPE_CTRL_STS	/;"	d
MAC_FSM_CONTROL	dwmac5.h	/^#define MAC_FSM_CONTROL	/;"	d
MAC_HASH_HIGH	dwmac100.h	/^#define MAC_HASH_HIGH	/;"	d
MAC_HASH_LOW	dwmac100.h	/^#define MAC_HASH_LOW	/;"	d
MAC_MII_ADDR	dwmac100.h	/^#define MAC_MII_ADDR	/;"	d
MAC_MII_ADDR_BUSY	dwmac100.h	/^#define MAC_MII_ADDR_BUSY	/;"	d
MAC_MII_ADDR_WRITE	dwmac100.h	/^#define MAC_MII_ADDR_WRITE	/;"	d
MAC_MII_DATA	dwmac100.h	/^#define MAC_MII_DATA	/;"	d
MAC_PPS_CONTROL	dwmac5.h	/^#define MAC_PPS_CONTROL	/;"	d
MAC_PPSx_INTERVAL	dwmac5.h	/^#define MAC_PPSx_INTERVAL(/;"	d
MAC_PPSx_TARGET_TIME_NSEC	dwmac5.h	/^#define MAC_PPSx_TARGET_TIME_NSEC(/;"	d
MAC_PPSx_TARGET_TIME_SEC	dwmac5.h	/^#define MAC_PPSx_TARGET_TIME_SEC(/;"	d
MAC_PPSx_WIDTH	dwmac5.h	/^#define MAC_PPSx_WIDTH(/;"	d
MAC_VLAN1	dwmac100.h	/^#define MAC_VLAN1	/;"	d
MAC_VLAN2	dwmac100.h	/^#define MAC_VLAN2	/;"	d
MAX_DMA_RIWT	common.h	/^#define MAX_DMA_RIWT	/;"	d
MCGRENx	dwmac5.h	/^#define MCGRENx(/;"	d
MCSIS	dwmac5.h	/^#define MCSIS	/;"	d
MECIS	dwmac5.h	/^#define MECIS	/;"	d
MESTEE	dwmac5.h	/^#define MESTEE	/;"	d
MEUIS	dwmac5.h	/^#define MEUIS	/;"	d
MII_BUSY	stmmac_mdio.c	/^#define MII_BUSY /;"	d	file:
MII_DATA_MASK	stmmac_mdio.c	/^#define MII_DATA_MASK /;"	d	file:
MII_GMAC4_C45E	stmmac_mdio.c	/^#define MII_GMAC4_C45E	/;"	d	file:
MII_GMAC4_GOC_SHIFT	stmmac_mdio.c	/^#define MII_GMAC4_GOC_SHIFT	/;"	d	file:
MII_GMAC4_READ	stmmac_mdio.c	/^#define MII_GMAC4_READ	/;"	d	file:
MII_GMAC4_REG_ADDR_SHIFT	stmmac_mdio.c	/^#define MII_GMAC4_REG_ADDR_SHIFT	/;"	d	file:
MII_GMAC4_WRITE	stmmac_mdio.c	/^#define MII_GMAC4_WRITE	/;"	d	file:
MII_PHY_SEL_MASK	dwmac-sti.c	/^#define MII_PHY_SEL_MASK	/;"	d	file:
MII_WRITE	stmmac_mdio.c	/^#define MII_WRITE /;"	d	file:
MII_XGMAC_BUSY	stmmac_mdio.c	/^#define MII_XGMAC_BUSY	/;"	d	file:
MII_XGMAC_C22P_MASK	stmmac_mdio.c	/^#define MII_XGMAC_C22P_MASK	/;"	d	file:
MII_XGMAC_CMD_SHIFT	stmmac_mdio.c	/^#define MII_XGMAC_CMD_SHIFT	/;"	d	file:
MII_XGMAC_DA_SHIFT	stmmac_mdio.c	/^#define MII_XGMAC_DA_SHIFT	/;"	d	file:
MII_XGMAC_MAX_C22ADDR	stmmac_mdio.c	/^#define MII_XGMAC_MAX_C22ADDR	/;"	d	file:
MII_XGMAC_PA_SHIFT	stmmac_mdio.c	/^#define MII_XGMAC_PA_SHIFT	/;"	d	file:
MII_XGMAC_READ	stmmac_mdio.c	/^#define MII_XGMAC_READ	/;"	d	file:
MII_XGMAC_SADDR	stmmac_mdio.c	/^#define MII_XGMAC_SADDR	/;"	d	file:
MII_XGMAC_WRITE	stmmac_mdio.c	/^#define MII_XGMAC_WRITE	/;"	d	file:
MIN_DMA_RIWT	common.h	/^#define MIN_DMA_RIWT	/;"	d
MMC_CNTRL	mmc_core.c	/^#define MMC_CNTRL	/;"	d	file:
MMC_CNTRL_COUNTER_FREEZER	mmc.h	/^#define MMC_CNTRL_COUNTER_FREEZER	/;"	d
MMC_CNTRL_COUNTER_RESET	mmc.h	/^#define MMC_CNTRL_COUNTER_RESET	/;"	d
MMC_CNTRL_COUNTER_STOP_ROLLOVER	mmc.h	/^#define MMC_CNTRL_COUNTER_STOP_ROLLOVER	/;"	d
MMC_CNTRL_FULL_HALF_PRESET	mmc.h	/^#define MMC_CNTRL_FULL_HALF_PRESET	/;"	d
MMC_CNTRL_PRESET	mmc.h	/^#define MMC_CNTRL_PRESET	/;"	d
MMC_CNTRL_RESET_ON_READ	mmc.h	/^#define MMC_CNTRL_RESET_ON_READ	/;"	d
MMC_DEFAULT_MASK	mmc_core.c	/^#define MMC_DEFAULT_MASK	/;"	d	file:
MMC_GMAC3_X_OFFSET	mmc.h	/^#define MMC_GMAC3_X_OFFSET	/;"	d
MMC_GMAC4_OFFSET	mmc.h	/^#define MMC_GMAC4_OFFSET	/;"	d
MMC_RX_1024_TO_MAX_OCTETS_GB	mmc_core.c	/^#define MMC_RX_1024_TO_MAX_OCTETS_GB	/;"	d	file:
MMC_RX_128_TO_255_OCTETS_GB	mmc_core.c	/^#define MMC_RX_128_TO_255_OCTETS_GB	/;"	d	file:
MMC_RX_256_TO_511_OCTETS_GB	mmc_core.c	/^#define MMC_RX_256_TO_511_OCTETS_GB	/;"	d	file:
MMC_RX_512_TO_1023_OCTETS_GB	mmc_core.c	/^#define MMC_RX_512_TO_1023_OCTETS_GB	/;"	d	file:
MMC_RX_64_OCTETS_GB	mmc_core.c	/^#define MMC_RX_64_OCTETS_GB	/;"	d	file:
MMC_RX_65_TO_127_OCTETS_GB	mmc_core.c	/^#define MMC_RX_65_TO_127_OCTETS_GB	/;"	d	file:
MMC_RX_ALIGN_ERROR	mmc_core.c	/^#define MMC_RX_ALIGN_ERROR	/;"	d	file:
MMC_RX_AUTOFRANGETYPE	mmc_core.c	/^#define MMC_RX_AUTOFRANGETYPE	/;"	d	file:
MMC_RX_BROADCASTFRAME_G	mmc_core.c	/^#define MMC_RX_BROADCASTFRAME_G	/;"	d	file:
MMC_RX_CRC_ERROR	mmc_core.c	/^#define MMC_RX_CRC_ERROR	/;"	d	file:
MMC_RX_FIFO_OVERFLOW	mmc_core.c	/^#define MMC_RX_FIFO_OVERFLOW	/;"	d	file:
MMC_RX_FPE_FRAG	mmc_core.c	/^#define MMC_RX_FPE_FRAG	/;"	d	file:
MMC_RX_FRAMECOUNT_GB	mmc_core.c	/^#define MMC_RX_FRAMECOUNT_GB	/;"	d	file:
MMC_RX_ICMP_ERR	mmc_core.c	/^#define MMC_RX_ICMP_ERR	/;"	d	file:
MMC_RX_ICMP_ERR_OCTETS	mmc_core.c	/^#define MMC_RX_ICMP_ERR_OCTETS	/;"	d	file:
MMC_RX_ICMP_GD	mmc_core.c	/^#define MMC_RX_ICMP_GD	/;"	d	file:
MMC_RX_ICMP_GD_OCTETS	mmc_core.c	/^#define MMC_RX_ICMP_GD_OCTETS	/;"	d	file:
MMC_RX_INTR	mmc_core.c	/^#define MMC_RX_INTR	/;"	d	file:
MMC_RX_INTR_MASK	mmc_core.c	/^#define MMC_RX_INTR_MASK	/;"	d	file:
MMC_RX_IPC_INTR	mmc_core.c	/^#define MMC_RX_IPC_INTR	/;"	d	file:
MMC_RX_IPC_INTR_MASK	mmc_core.c	/^#define MMC_RX_IPC_INTR_MASK	/;"	d	file:
MMC_RX_IPV4_FRAG	mmc_core.c	/^#define MMC_RX_IPV4_FRAG	/;"	d	file:
MMC_RX_IPV4_FRAG_OCTETS	mmc_core.c	/^#define MMC_RX_IPV4_FRAG_OCTETS	/;"	d	file:
MMC_RX_IPV4_GD	mmc_core.c	/^#define MMC_RX_IPV4_GD	/;"	d	file:
MMC_RX_IPV4_GD_OCTETS	mmc_core.c	/^#define MMC_RX_IPV4_GD_OCTETS	/;"	d	file:
MMC_RX_IPV4_HDERR	mmc_core.c	/^#define MMC_RX_IPV4_HDERR	/;"	d	file:
MMC_RX_IPV4_HDERR_OCTETS	mmc_core.c	/^#define MMC_RX_IPV4_HDERR_OCTETS	/;"	d	file:
MMC_RX_IPV4_NOPAY	mmc_core.c	/^#define MMC_RX_IPV4_NOPAY	/;"	d	file:
MMC_RX_IPV4_NOPAY_OCTETS	mmc_core.c	/^#define MMC_RX_IPV4_NOPAY_OCTETS	/;"	d	file:
MMC_RX_IPV4_UDSBL	mmc_core.c	/^#define MMC_RX_IPV4_UDSBL	/;"	d	file:
MMC_RX_IPV4_UDSBL_OCTETS	mmc_core.c	/^#define MMC_RX_IPV4_UDSBL_OCTETS	/;"	d	file:
MMC_RX_IPV6_GD	mmc_core.c	/^#define MMC_RX_IPV6_GD	/;"	d	file:
MMC_RX_IPV6_GD_OCTETS	mmc_core.c	/^#define MMC_RX_IPV6_GD_OCTETS	/;"	d	file:
MMC_RX_IPV6_HDERR	mmc_core.c	/^#define MMC_RX_IPV6_HDERR	/;"	d	file:
MMC_RX_IPV6_HDERR_OCTETS	mmc_core.c	/^#define MMC_RX_IPV6_HDERR_OCTETS	/;"	d	file:
MMC_RX_IPV6_NOPAY	mmc_core.c	/^#define MMC_RX_IPV6_NOPAY	/;"	d	file:
MMC_RX_IPV6_NOPAY_OCTETS	mmc_core.c	/^#define MMC_RX_IPV6_NOPAY_OCTETS	/;"	d	file:
MMC_RX_JABBER_ERROR	mmc_core.c	/^#define MMC_RX_JABBER_ERROR	/;"	d	file:
MMC_RX_LENGTH_ERROR	mmc_core.c	/^#define MMC_RX_LENGTH_ERROR	/;"	d	file:
MMC_RX_MULTICASTFRAME_G	mmc_core.c	/^#define MMC_RX_MULTICASTFRAME_G	/;"	d	file:
MMC_RX_OCTETCOUNT_G	mmc_core.c	/^#define MMC_RX_OCTETCOUNT_G	/;"	d	file:
MMC_RX_OCTETCOUNT_GB	mmc_core.c	/^#define MMC_RX_OCTETCOUNT_GB	/;"	d	file:
MMC_RX_OVERSIZE_G	mmc_core.c	/^#define MMC_RX_OVERSIZE_G	/;"	d	file:
MMC_RX_PAUSE_FRAMES	mmc_core.c	/^#define MMC_RX_PAUSE_FRAMES	/;"	d	file:
MMC_RX_PKT_ASSEMBLY_ERR	mmc_core.c	/^#define MMC_RX_PKT_ASSEMBLY_ERR	/;"	d	file:
MMC_RX_PKT_ASSEMBLY_OK	mmc_core.c	/^#define MMC_RX_PKT_ASSEMBLY_OK	/;"	d	file:
MMC_RX_PKT_SMD_ERR	mmc_core.c	/^#define MMC_RX_PKT_SMD_ERR	/;"	d	file:
MMC_RX_RUN_ERROR	mmc_core.c	/^#define MMC_RX_RUN_ERROR	/;"	d	file:
MMC_RX_TCP_ERR	mmc_core.c	/^#define MMC_RX_TCP_ERR	/;"	d	file:
MMC_RX_TCP_ERR_OCTETS	mmc_core.c	/^#define MMC_RX_TCP_ERR_OCTETS	/;"	d	file:
MMC_RX_TCP_GD	mmc_core.c	/^#define MMC_RX_TCP_GD	/;"	d	file:
MMC_RX_TCP_GD_OCTETS	mmc_core.c	/^#define MMC_RX_TCP_GD_OCTETS	/;"	d	file:
MMC_RX_UDP_ERR	mmc_core.c	/^#define MMC_RX_UDP_ERR	/;"	d	file:
MMC_RX_UDP_ERR_OCTETS	mmc_core.c	/^#define MMC_RX_UDP_ERR_OCTETS	/;"	d	file:
MMC_RX_UDP_GD	mmc_core.c	/^#define MMC_RX_UDP_GD	/;"	d	file:
MMC_RX_UDP_GD_OCTETS	mmc_core.c	/^#define MMC_RX_UDP_GD_OCTETS	/;"	d	file:
MMC_RX_UNDERSIZE_G	mmc_core.c	/^#define MMC_RX_UNDERSIZE_G	/;"	d	file:
MMC_RX_UNICAST_G	mmc_core.c	/^#define MMC_RX_UNICAST_G	/;"	d	file:
MMC_RX_VLAN_FRAMES_GB	mmc_core.c	/^#define MMC_RX_VLAN_FRAMES_GB	/;"	d	file:
MMC_RX_WATCHDOG_ERROR	mmc_core.c	/^#define MMC_RX_WATCHDOG_ERROR	/;"	d	file:
MMC_TX_1024_TO_MAX_OCTETS_GB	mmc_core.c	/^#define MMC_TX_1024_TO_MAX_OCTETS_GB	/;"	d	file:
MMC_TX_128_TO_255_OCTETS_GB	mmc_core.c	/^#define MMC_TX_128_TO_255_OCTETS_GB	/;"	d	file:
MMC_TX_256_TO_511_OCTETS_GB	mmc_core.c	/^#define MMC_TX_256_TO_511_OCTETS_GB	/;"	d	file:
MMC_TX_512_TO_1023_OCTETS_GB	mmc_core.c	/^#define MMC_TX_512_TO_1023_OCTETS_GB	/;"	d	file:
MMC_TX_64_OCTETS_GB	mmc_core.c	/^#define MMC_TX_64_OCTETS_GB	/;"	d	file:
MMC_TX_65_TO_127_OCTETS_GB	mmc_core.c	/^#define MMC_TX_65_TO_127_OCTETS_GB	/;"	d	file:
MMC_TX_BROADCASTFRAME_G	mmc_core.c	/^#define MMC_TX_BROADCASTFRAME_G	/;"	d	file:
MMC_TX_BROADCAST_GB	mmc_core.c	/^#define MMC_TX_BROADCAST_GB	/;"	d	file:
MMC_TX_CARRIER_ERROR	mmc_core.c	/^#define MMC_TX_CARRIER_ERROR	/;"	d	file:
MMC_TX_DEFERRED	mmc_core.c	/^#define MMC_TX_DEFERRED	/;"	d	file:
MMC_TX_EXCESSDEF	mmc_core.c	/^#define MMC_TX_EXCESSDEF	/;"	d	file:
MMC_TX_EXESSCOL	mmc_core.c	/^#define MMC_TX_EXESSCOL	/;"	d	file:
MMC_TX_FPE_FRAG	mmc_core.c	/^#define MMC_TX_FPE_FRAG	/;"	d	file:
MMC_TX_FRAMECOUNT_G	mmc_core.c	/^#define MMC_TX_FRAMECOUNT_G	/;"	d	file:
MMC_TX_FRAMECOUNT_GB	mmc_core.c	/^#define MMC_TX_FRAMECOUNT_GB	/;"	d	file:
MMC_TX_HOLD_REQ	mmc_core.c	/^#define MMC_TX_HOLD_REQ	/;"	d	file:
MMC_TX_INTR	mmc_core.c	/^#define MMC_TX_INTR	/;"	d	file:
MMC_TX_INTR_MASK	mmc_core.c	/^#define MMC_TX_INTR_MASK	/;"	d	file:
MMC_TX_LATECOL	mmc_core.c	/^#define MMC_TX_LATECOL	/;"	d	file:
MMC_TX_MULTICASTFRAME_G	mmc_core.c	/^#define MMC_TX_MULTICASTFRAME_G	/;"	d	file:
MMC_TX_MULTICAST_GB	mmc_core.c	/^#define MMC_TX_MULTICAST_GB	/;"	d	file:
MMC_TX_MULTICOL_G	mmc_core.c	/^#define MMC_TX_MULTICOL_G	/;"	d	file:
MMC_TX_OCTETCOUNT_G	mmc_core.c	/^#define MMC_TX_OCTETCOUNT_G	/;"	d	file:
MMC_TX_OCTETCOUNT_GB	mmc_core.c	/^#define MMC_TX_OCTETCOUNT_GB	/;"	d	file:
MMC_TX_PAUSE_FRAME	mmc_core.c	/^#define MMC_TX_PAUSE_FRAME	/;"	d	file:
MMC_TX_SINGLECOL_G	mmc_core.c	/^#define MMC_TX_SINGLECOL_G	/;"	d	file:
MMC_TX_UNDERFLOW_ERROR	mmc_core.c	/^#define MMC_TX_UNDERFLOW_ERROR	/;"	d	file:
MMC_TX_UNICAST_GB	mmc_core.c	/^#define MMC_TX_UNICAST_GB	/;"	d	file:
MMC_TX_VLAN_FRAME_G	mmc_core.c	/^#define MMC_TX_VLAN_FRAME_G	/;"	d	file:
MMC_XGMAC_OFFSET	mmc.h	/^#define MMC_XGMAC_OFFSET	/;"	d
MMC_XGMAC_RX_1024OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_1024OCT_GB	/;"	d	file:
MMC_XGMAC_RX_128OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_128OCT_GB	/;"	d	file:
MMC_XGMAC_RX_256OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_256OCT_GB	/;"	d	file:
MMC_XGMAC_RX_512OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_512OCT_GB	/;"	d	file:
MMC_XGMAC_RX_64OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_64OCT_GB	/;"	d	file:
MMC_XGMAC_RX_65OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_65OCT_GB	/;"	d	file:
MMC_XGMAC_RX_ALIGN_ERR_PKT	mmc_core.c	/^#define MMC_XGMAC_RX_ALIGN_ERR_PKT	/;"	d	file:
MMC_XGMAC_RX_BROAD_PKT_G	mmc_core.c	/^#define MMC_XGMAC_RX_BROAD_PKT_G	/;"	d	file:
MMC_XGMAC_RX_CRC_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_CRC_ERR	/;"	d	file:
MMC_XGMAC_RX_DISCARD_OCT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_DISCARD_OCT_GB	/;"	d	file:
MMC_XGMAC_RX_DISCARD_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_DISCARD_PKT_GB	/;"	d	file:
MMC_XGMAC_RX_FIFOOVER_PKT	mmc_core.c	/^#define MMC_XGMAC_RX_FIFOOVER_PKT	/;"	d	file:
MMC_XGMAC_RX_FPE_FRAG	mmc_core.c	/^#define MMC_XGMAC_RX_FPE_FRAG	/;"	d	file:
MMC_XGMAC_RX_IPC_INTR_MASK	mmc_core.c	/^#define MMC_XGMAC_RX_IPC_INTR_MASK	/;"	d	file:
MMC_XGMAC_RX_JABBER_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_JABBER_ERR	/;"	d	file:
MMC_XGMAC_RX_LENGTH_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_LENGTH_ERR	/;"	d	file:
MMC_XGMAC_RX_LPI_TRAN	mmc_core.c	/^#define MMC_XGMAC_RX_LPI_TRAN	/;"	d	file:
MMC_XGMAC_RX_LPI_USEC	mmc_core.c	/^#define MMC_XGMAC_RX_LPI_USEC	/;"	d	file:
MMC_XGMAC_RX_MULTI_PKT_G	mmc_core.c	/^#define MMC_XGMAC_RX_MULTI_PKT_G	/;"	d	file:
MMC_XGMAC_RX_OCTET_G	mmc_core.c	/^#define MMC_XGMAC_RX_OCTET_G	/;"	d	file:
MMC_XGMAC_RX_OCTET_GB	mmc_core.c	/^#define MMC_XGMAC_RX_OCTET_GB	/;"	d	file:
MMC_XGMAC_RX_OVER	mmc_core.c	/^#define MMC_XGMAC_RX_OVER	/;"	d	file:
MMC_XGMAC_RX_PAUSE	mmc_core.c	/^#define MMC_XGMAC_RX_PAUSE	/;"	d	file:
MMC_XGMAC_RX_PKT_ASSEMBLY_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR	/;"	d	file:
MMC_XGMAC_RX_PKT_ASSEMBLY_OK	mmc_core.c	/^#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK	/;"	d	file:
MMC_XGMAC_RX_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_PKT_GB	/;"	d	file:
MMC_XGMAC_RX_PKT_SMD_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_PKT_SMD_ERR	/;"	d	file:
MMC_XGMAC_RX_RANGE	mmc_core.c	/^#define MMC_XGMAC_RX_RANGE	/;"	d	file:
MMC_XGMAC_RX_RUNT_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_RUNT_ERR	/;"	d	file:
MMC_XGMAC_RX_UNDER	mmc_core.c	/^#define MMC_XGMAC_RX_UNDER	/;"	d	file:
MMC_XGMAC_RX_UNI_PKT_G	mmc_core.c	/^#define MMC_XGMAC_RX_UNI_PKT_G	/;"	d	file:
MMC_XGMAC_RX_VLAN_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_RX_VLAN_PKT_GB	/;"	d	file:
MMC_XGMAC_RX_WATCHDOG_ERR	mmc_core.c	/^#define MMC_XGMAC_RX_WATCHDOG_ERR	/;"	d	file:
MMC_XGMAC_TX_1024OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_1024OCT_GB	/;"	d	file:
MMC_XGMAC_TX_128OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_128OCT_GB	/;"	d	file:
MMC_XGMAC_TX_256OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_256OCT_GB	/;"	d	file:
MMC_XGMAC_TX_512OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_512OCT_GB	/;"	d	file:
MMC_XGMAC_TX_64OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_64OCT_GB	/;"	d	file:
MMC_XGMAC_TX_65OCT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_65OCT_GB	/;"	d	file:
MMC_XGMAC_TX_BROAD_PKT_G	mmc_core.c	/^#define MMC_XGMAC_TX_BROAD_PKT_G	/;"	d	file:
MMC_XGMAC_TX_BROAD_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_BROAD_PKT_GB	/;"	d	file:
MMC_XGMAC_TX_FPE_FRAG	mmc_core.c	/^#define MMC_XGMAC_TX_FPE_FRAG	/;"	d	file:
MMC_XGMAC_TX_HOLD_REQ	mmc_core.c	/^#define MMC_XGMAC_TX_HOLD_REQ	/;"	d	file:
MMC_XGMAC_TX_LPI_TRAN	mmc_core.c	/^#define MMC_XGMAC_TX_LPI_TRAN	/;"	d	file:
MMC_XGMAC_TX_LPI_USEC	mmc_core.c	/^#define MMC_XGMAC_TX_LPI_USEC	/;"	d	file:
MMC_XGMAC_TX_MULTI_PKT_G	mmc_core.c	/^#define MMC_XGMAC_TX_MULTI_PKT_G	/;"	d	file:
MMC_XGMAC_TX_MULTI_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_MULTI_PKT_GB	/;"	d	file:
MMC_XGMAC_TX_OCTET_G	mmc_core.c	/^#define MMC_XGMAC_TX_OCTET_G	/;"	d	file:
MMC_XGMAC_TX_OCTET_GB	mmc_core.c	/^#define MMC_XGMAC_TX_OCTET_GB	/;"	d	file:
MMC_XGMAC_TX_PAUSE	mmc_core.c	/^#define MMC_XGMAC_TX_PAUSE	/;"	d	file:
MMC_XGMAC_TX_PKT_G	mmc_core.c	/^#define MMC_XGMAC_TX_PKT_G	/;"	d	file:
MMC_XGMAC_TX_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_PKT_GB	/;"	d	file:
MMC_XGMAC_TX_UNDER	mmc_core.c	/^#define MMC_XGMAC_TX_UNDER	/;"	d	file:
MMC_XGMAC_TX_UNI_PKT_GB	mmc_core.c	/^#define MMC_XGMAC_TX_UNI_PKT_GB	/;"	d	file:
MMC_XGMAC_TX_VLAN_PKT_G	mmc_core.c	/^#define MMC_XGMAC_TX_VLAN_PKT_G	/;"	d	file:
MODULE_NAME	dkms.conf	/^MODULE_NAME="stmmac"$/;"	k
MRXEE	dwmac5.h	/^#define MRXEE	/;"	d
MRXPEE	dwmac5.h	/^#define MRXPEE	/;"	d
MSCIS	dwmac5.h	/^#define MSCIS	/;"	d
MSUIS	dwmac5.h	/^#define MSUIS	/;"	d
MTL_CHANX_BASE_ADDR	dwmac4.h	/^#define MTL_CHANX_BASE_ADDR(/;"	d
MTL_CHAN_BASE_ADDR	dwmac4.h	/^#define MTL_CHAN_BASE_ADDR	/;"	d
MTL_CHAN_BASE_OFFSET	dwmac4.h	/^#define MTL_CHAN_BASE_OFFSET	/;"	d
MTL_CHAN_INT_CTRL	dwmac4.h	/^#define MTL_CHAN_INT_CTRL(/;"	d
MTL_CHAN_RX_DEBUG	dwmac4.h	/^#define MTL_CHAN_RX_DEBUG(/;"	d
MTL_CHAN_RX_OP_MODE	dwmac4.h	/^#define MTL_CHAN_RX_OP_MODE(/;"	d
MTL_CHAN_TX_DEBUG	dwmac4.h	/^#define MTL_CHAN_TX_DEBUG(/;"	d
MTL_CHAN_TX_OP_MODE	dwmac4.h	/^#define MTL_CHAN_TX_OP_MODE(/;"	d
MTL_DEBUG_RRCSTS_FLUSH	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_FLUSH	/;"	d
MTL_DEBUG_RRCSTS_IDLE	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_IDLE	/;"	d
MTL_DEBUG_RRCSTS_MASK	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_MASK	/;"	d
MTL_DEBUG_RRCSTS_RDATA	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_RDATA	/;"	d
MTL_DEBUG_RRCSTS_RSTAT	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_RSTAT	/;"	d
MTL_DEBUG_RRCSTS_SHIFT	dwmac4.h	/^#define MTL_DEBUG_RRCSTS_SHIFT	/;"	d
MTL_DEBUG_RWCSTS	dwmac4.h	/^#define MTL_DEBUG_RWCSTS	/;"	d
MTL_DEBUG_RXFSTS_AT	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_AT	/;"	d
MTL_DEBUG_RXFSTS_BT	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_BT	/;"	d
MTL_DEBUG_RXFSTS_EMPTY	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_EMPTY	/;"	d
MTL_DEBUG_RXFSTS_FULL	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_FULL	/;"	d
MTL_DEBUG_RXFSTS_MASK	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_MASK	/;"	d
MTL_DEBUG_RXFSTS_SHIFT	dwmac4.h	/^#define MTL_DEBUG_RXFSTS_SHIFT	/;"	d
MTL_DEBUG_TRCSTS_IDLE	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_IDLE	/;"	d
MTL_DEBUG_TRCSTS_MASK	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_MASK	/;"	d
MTL_DEBUG_TRCSTS_READ	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_READ	/;"	d
MTL_DEBUG_TRCSTS_SHIFT	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_SHIFT	/;"	d
MTL_DEBUG_TRCSTS_TXW	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_TXW	/;"	d
MTL_DEBUG_TRCSTS_WRITE	dwmac4.h	/^#define MTL_DEBUG_TRCSTS_WRITE	/;"	d
MTL_DEBUG_TWCSTS	dwmac4.h	/^#define MTL_DEBUG_TWCSTS	/;"	d
MTL_DEBUG_TXFSTS	dwmac4.h	/^#define MTL_DEBUG_TXFSTS	/;"	d
MTL_DEBUG_TXPAUSED	dwmac4.h	/^#define MTL_DEBUG_TXPAUSED	/;"	d
MTL_DEBUG_TXSTSFSTS	dwmac4.h	/^#define MTL_DEBUG_TXSTSFSTS	/;"	d
MTL_DPP_CONTROL	dwmac5.h	/^#define MTL_DPP_CONTROL	/;"	d
MTL_ECC_CONTROL	dwmac5.h	/^#define MTL_ECC_CONTROL	/;"	d
MTL_ECC_INT_ENABLE	dwmac5.h	/^#define MTL_ECC_INT_ENABLE	/;"	d
MTL_ECC_INT_STATUS	dwmac5.h	/^#define MTL_ECC_INT_STATUS	/;"	d
MTL_EST_CONTROL	dwmac5.h	/^#define MTL_EST_CONTROL	/;"	d
MTL_EST_GCL_CONTROL	dwmac5.h	/^#define MTL_EST_GCL_CONTROL	/;"	d
MTL_EST_GCL_DATA	dwmac5.h	/^#define MTL_EST_GCL_DATA	/;"	d
MTL_ETSX_CTRL_BASE_ADDR	dwmac4.h	/^#define MTL_ETSX_CTRL_BASE_ADDR(/;"	d
MTL_ETS_CTRL_AVALG	dwmac4.h	/^#define MTL_ETS_CTRL_AVALG	/;"	d
MTL_ETS_CTRL_BASE_ADDR	dwmac4.h	/^#define MTL_ETS_CTRL_BASE_ADDR	/;"	d
MTL_ETS_CTRL_BASE_OFFSET	dwmac4.h	/^#define MTL_ETS_CTRL_BASE_OFFSET	/;"	d
MTL_ETS_CTRL_CC	dwmac4.h	/^#define MTL_ETS_CTRL_CC	/;"	d
MTL_FRPE	dwmac4.h	/^#define MTL_FRPE	/;"	d
MTL_HIGH_CREDX_BASE_ADDR	dwmac4.h	/^#define MTL_HIGH_CREDX_BASE_ADDR(/;"	d
MTL_HIGH_CRED_BASE_ADDR	dwmac4.h	/^#define MTL_HIGH_CRED_BASE_ADDR	/;"	d
MTL_HIGH_CRED_HC_MASK	dwmac4.h	/^#define MTL_HIGH_CRED_HC_MASK	/;"	d
MTL_HIGH_CRED_LC_MASK	dwmac4.h	/^#define MTL_HIGH_CRED_LC_MASK	/;"	d
MTL_HIGH_CRED_OFFSET	dwmac4.h	/^#define MTL_HIGH_CRED_OFFSET	/;"	d
MTL_INT_QX	dwmac4.h	/^#define MTL_INT_QX(/;"	d
MTL_INT_STATUS	dwmac4.h	/^#define MTL_INT_STATUS	/;"	d
MTL_LOW_CREDX_BASE_ADDR	dwmac4.h	/^#define MTL_LOW_CREDX_BASE_ADDR(/;"	d
MTL_LOW_CRED_BASE_ADDR	dwmac4.h	/^#define MTL_LOW_CRED_BASE_ADDR	/;"	d
MTL_LOW_CRED_OFFSET	dwmac4.h	/^#define MTL_LOW_CRED_OFFSET	/;"	d
MTL_OPERATION_MODE	dwmac4.h	/^#define MTL_OPERATION_MODE	/;"	d
MTL_OPERATION_RAA	dwmac4.h	/^#define MTL_OPERATION_RAA	/;"	d
MTL_OPERATION_RAA_SP	dwmac4.h	/^#define MTL_OPERATION_RAA_SP	/;"	d
MTL_OPERATION_RAA_WSP	dwmac4.h	/^#define MTL_OPERATION_RAA_WSP	/;"	d
MTL_OPERATION_SCHALG_DWRR	dwmac4.h	/^#define MTL_OPERATION_SCHALG_DWRR	/;"	d
MTL_OPERATION_SCHALG_MASK	dwmac4.h	/^#define MTL_OPERATION_SCHALG_MASK	/;"	d
MTL_OPERATION_SCHALG_SP	dwmac4.h	/^#define MTL_OPERATION_SCHALG_SP	/;"	d
MTL_OPERATION_SCHALG_WFQ	dwmac4.h	/^#define MTL_OPERATION_SCHALG_WFQ	/;"	d
MTL_OPERATION_SCHALG_WRR	dwmac4.h	/^#define MTL_OPERATION_SCHALG_WRR	/;"	d
MTL_OP_MODE_EHFC	dwmac4.h	/^#define MTL_OP_MODE_EHFC	/;"	d
MTL_OP_MODE_RFA_MASK	dwmac4.h	/^#define MTL_OP_MODE_RFA_MASK	/;"	d
MTL_OP_MODE_RFA_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_RFA_SHIFT	/;"	d
MTL_OP_MODE_RFD_MASK	dwmac4.h	/^#define MTL_OP_MODE_RFD_MASK	/;"	d
MTL_OP_MODE_RFD_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_RFD_SHIFT	/;"	d
MTL_OP_MODE_RQS_MASK	dwmac4.h	/^#define MTL_OP_MODE_RQS_MASK	/;"	d
MTL_OP_MODE_RQS_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_RQS_SHIFT	/;"	d
MTL_OP_MODE_RSF	dwmac4.h	/^#define MTL_OP_MODE_RSF	/;"	d
MTL_OP_MODE_RTC_128	dwmac4.h	/^#define MTL_OP_MODE_RTC_128	/;"	d
MTL_OP_MODE_RTC_32	dwmac4.h	/^#define MTL_OP_MODE_RTC_32	/;"	d
MTL_OP_MODE_RTC_64	dwmac4.h	/^#define MTL_OP_MODE_RTC_64	/;"	d
MTL_OP_MODE_RTC_96	dwmac4.h	/^#define MTL_OP_MODE_RTC_96	/;"	d
MTL_OP_MODE_RTC_MASK	dwmac4.h	/^#define MTL_OP_MODE_RTC_MASK	/;"	d
MTL_OP_MODE_RTC_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_RTC_SHIFT	/;"	d
MTL_OP_MODE_TQS_MASK	dwmac4.h	/^#define MTL_OP_MODE_TQS_MASK	/;"	d
MTL_OP_MODE_TQS_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_TQS_SHIFT	/;"	d
MTL_OP_MODE_TSF	dwmac4.h	/^#define MTL_OP_MODE_TSF	/;"	d
MTL_OP_MODE_TTC_128	dwmac4.h	/^#define MTL_OP_MODE_TTC_128	/;"	d
MTL_OP_MODE_TTC_192	dwmac4.h	/^#define MTL_OP_MODE_TTC_192	/;"	d
MTL_OP_MODE_TTC_256	dwmac4.h	/^#define MTL_OP_MODE_TTC_256	/;"	d
MTL_OP_MODE_TTC_32	dwmac4.h	/^#define MTL_OP_MODE_TTC_32	/;"	d
MTL_OP_MODE_TTC_384	dwmac4.h	/^#define MTL_OP_MODE_TTC_384	/;"	d
MTL_OP_MODE_TTC_512	dwmac4.h	/^#define MTL_OP_MODE_TTC_512	/;"	d
MTL_OP_MODE_TTC_64	dwmac4.h	/^#define MTL_OP_MODE_TTC_64	/;"	d
MTL_OP_MODE_TTC_96	dwmac4.h	/^#define MTL_OP_MODE_TTC_96	/;"	d
MTL_OP_MODE_TTC_MASK	dwmac4.h	/^#define MTL_OP_MODE_TTC_MASK	/;"	d
MTL_OP_MODE_TTC_SHIFT	dwmac4.h	/^#define MTL_OP_MODE_TTC_SHIFT	/;"	d
MTL_OP_MODE_TXQEN	dwmac4.h	/^#define MTL_OP_MODE_TXQEN	/;"	d
MTL_OP_MODE_TXQEN_AV	dwmac4.h	/^#define MTL_OP_MODE_TXQEN_AV	/;"	d
MTL_OP_MODE_TXQEN_MASK	dwmac4.h	/^#define MTL_OP_MODE_TXQEN_MASK	/;"	d
MTL_RXP_CONTROL_STATUS	dwmac5.h	/^#define MTL_RXP_CONTROL_STATUS	/;"	d
MTL_RXP_IACC_CTRL_STATUS	dwmac5.h	/^#define MTL_RXP_IACC_CTRL_STATUS	/;"	d
MTL_RXP_IACC_DATA	dwmac5.h	/^#define MTL_RXP_IACC_DATA	/;"	d
MTL_RXQ_DMA_MAP0	dwmac4.h	/^#define MTL_RXQ_DMA_MAP0	/;"	d
MTL_RXQ_DMA_MAP1	dwmac4.h	/^#define MTL_RXQ_DMA_MAP1	/;"	d
MTL_RXQ_DMA_Q04MDMACH	dwmac4.h	/^#define MTL_RXQ_DMA_Q04MDMACH(/;"	d
MTL_RXQ_DMA_Q04MDMACH_MASK	dwmac4.h	/^#define MTL_RXQ_DMA_Q04MDMACH_MASK	/;"	d
MTL_RXQ_DMA_QXMDMACH	dwmac4.h	/^#define MTL_RXQ_DMA_QXMDMACH(/;"	d
MTL_RXQ_DMA_QXMDMACH_MASK	dwmac4.h	/^#define MTL_RXQ_DMA_QXMDMACH_MASK(/;"	d
MTL_RX_OVERFLOW_INT	dwmac4.h	/^#define MTL_RX_OVERFLOW_INT	/;"	d
MTL_RX_OVERFLOW_INT_EN	dwmac4.h	/^#define MTL_RX_OVERFLOW_INT_EN	/;"	d
MTL_SAFETY_INT_STATUS	dwmac5.h	/^#define MTL_SAFETY_INT_STATUS	/;"	d
MTL_SEND_SLP_CREDX_BASE_ADDR	dwmac4.h	/^#define MTL_SEND_SLP_CREDX_BASE_ADDR(/;"	d
MTL_SEND_SLP_CRED_BASE_ADDR	dwmac4.h	/^#define MTL_SEND_SLP_CRED_BASE_ADDR	/;"	d
MTL_SEND_SLP_CRED_OFFSET	dwmac4.h	/^#define MTL_SEND_SLP_CRED_OFFSET	/;"	d
MTL_SEND_SLP_CRED_SSC_MASK	dwmac4.h	/^#define MTL_SEND_SLP_CRED_SSC_MASK	/;"	d
MTL_TXQX_WEIGHT_BASE_ADDR	dwmac4.h	/^#define MTL_TXQX_WEIGHT_BASE_ADDR(/;"	d
MTL_TXQ_WEIGHT_BASE_ADDR	dwmac4.h	/^#define MTL_TXQ_WEIGHT_BASE_ADDR	/;"	d
MTL_TXQ_WEIGHT_BASE_OFFSET	dwmac4.h	/^#define MTL_TXQ_WEIGHT_BASE_OFFSET	/;"	d
MTL_TXQ_WEIGHT_ISCQW_MASK	dwmac4.h	/^#define MTL_TXQ_WEIGHT_ISCQW_MASK	/;"	d
MTXEE	dwmac5.h	/^#define MTXEE	/;"	d
NPE	dwmac5.h	/^#define NPE	/;"	d
NSS_COMMON_CLK_DIV0	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV0	/;"	d	file:
NSS_COMMON_CLK_DIV_MASK	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_MASK	/;"	d	file:
NSS_COMMON_CLK_DIV_OFFSET	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_OFFSET(/;"	d	file:
NSS_COMMON_CLK_DIV_RGMII_10	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_RGMII_10	/;"	d	file:
NSS_COMMON_CLK_DIV_RGMII_100	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_RGMII_100	/;"	d	file:
NSS_COMMON_CLK_DIV_RGMII_1000	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_RGMII_1000	/;"	d	file:
NSS_COMMON_CLK_DIV_SGMII_10	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_SGMII_10	/;"	d	file:
NSS_COMMON_CLK_DIV_SGMII_100	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_SGMII_100	/;"	d	file:
NSS_COMMON_CLK_DIV_SGMII_1000	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_DIV_SGMII_1000	/;"	d	file:
NSS_COMMON_CLK_GATE	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE	/;"	d	file:
NSS_COMMON_CLK_GATE_GMII_RX_EN	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE_GMII_RX_EN(/;"	d	file:
NSS_COMMON_CLK_GATE_GMII_TX_EN	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE_GMII_TX_EN(/;"	d	file:
NSS_COMMON_CLK_GATE_PTP_EN	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE_PTP_EN(/;"	d	file:
NSS_COMMON_CLK_GATE_RGMII_RX_EN	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(/;"	d	file:
NSS_COMMON_CLK_GATE_RGMII_TX_EN	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(/;"	d	file:
NSS_COMMON_CLK_SRC_CTRL	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_SRC_CTRL	/;"	d	file:
NSS_COMMON_CLK_SRC_CTRL_OFFSET	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(/;"	d	file:
NSS_COMMON_CLK_SRC_CTRL_RGMII	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_SRC_CTRL_RGMII(/;"	d	file:
NSS_COMMON_CLK_SRC_CTRL_SGMII	dwmac-ipq806x.c	/^#define NSS_COMMON_CLK_SRC_CTRL_SGMII(/;"	d	file:
NSS_COMMON_GMAC_CTL	dwmac-ipq806x.c	/^#define NSS_COMMON_GMAC_CTL(/;"	d	file:
NSS_COMMON_GMAC_CTL_CSYS_REQ	dwmac-ipq806x.c	/^#define NSS_COMMON_GMAC_CTL_CSYS_REQ	/;"	d	file:
NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET	dwmac-ipq806x.c	/^#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET	/;"	d	file:
NSS_COMMON_GMAC_CTL_IFG_OFFSET	dwmac-ipq806x.c	/^#define NSS_COMMON_GMAC_CTL_IFG_OFFSET	/;"	d	file:
NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL	dwmac-ipq806x.c	/^#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL	/;"	d	file:
NUM_DWMAC1000_DMA_REGS	dwmac_dma.h	/^#define NUM_DWMAC1000_DMA_REGS	/;"	d
NUM_DWMAC100_DMA_REGS	dwmac_dma.h	/^#define NUM_DWMAC100_DMA_REGS	/;"	d
NVE	dwmac5.h	/^#define NVE	/;"	d
OPE	dwmac5.h	/^#define OPE	/;"	d
OXNAS_DWMAC_CTRL_REGOFFSET	dwmac-oxnas.c	/^#define OXNAS_DWMAC_CTRL_REGOFFSET	/;"	d	file:
OXNAS_DWMAC_DELAY_REGOFFSET	dwmac-oxnas.c	/^#define OXNAS_DWMAC_DELAY_REGOFFSET	/;"	d	file:
PACKAGE_NAME	dkms.conf	/^PACKAGE_NAME="stmmac"$/;"	k
PACKAGE_VERSION	dkms.conf	/^PACKAGE_VERSION="1.0.0atzlinux"$/;"	k
PACKET_AVCPQ	common.h	/^	PACKET_AVCPQ = 0x1, \/* AV Untagged Control packets *\/$/;"	e	enum:packets_types
PACKET_DCBCPQ	common.h	/^	PACKET_DCBCPQ = 0x3, \/* DCB Control Packets *\/$/;"	e	enum:packets_types
PACKET_MCBCQ	common.h	/^	PACKET_MCBCQ = 0x5, \/* Multicast & Broadcast Packets *\/$/;"	e	enum:packets_types
PACKET_PTPQ	common.h	/^	PACKET_PTPQ = 0x2, \/* PTP Packets *\/$/;"	e	enum:packets_types
PACKET_UPQ	common.h	/^	PACKET_UPQ = 0x4, \/* Untagged Packets *\/$/;"	e	enum:packets_types
PAUSE_TIME	common.h	/^#define PAUSE_TIME /;"	d
PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_QUARK_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_QUARK_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID	/;"	d	file:
PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID	dwmac-intel.c	/^#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID	/;"	d	file:
PCI_DEVICE_ID_STMMAC_STMMAC	stmmac_pci.c	/^#define PCI_DEVICE_ID_STMMAC_STMMAC	/;"	d	file:
PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID	stmmac_pci.c	/^#define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID	/;"	d	file:
PCI_VENDOR_ID_STMMAC	stmmac_pci.c	/^#define PCI_VENDOR_ID_STMMAC	/;"	d	file:
PCS_ANE_IRQ	common.h	/^#define	PCS_ANE_IRQ	/;"	d
PCS_LINK_IRQ	common.h	/^#define	PCS_LINK_IRQ	/;"	d
PCS_RGSMIIIS_IRQ	common.h	/^#define	PCS_RGSMIIIS_IRQ	/;"	d
PERI_ETH_DLY	dwmac-mediatek.c	/^#define PERI_ETH_DLY	/;"	d	file:
PERI_ETH_DLY_FINE	dwmac-mediatek.c	/^#define PERI_ETH_DLY_FINE	/;"	d	file:
PERI_ETH_PHY_INTF_SEL	dwmac-mediatek.c	/^#define PERI_ETH_PHY_INTF_SEL	/;"	d	file:
PHY_INTF_MII	dwmac-mediatek.c	/^#define PHY_INTF_MII	/;"	d	file:
PHY_INTF_RGMII	dwmac-mediatek.c	/^#define PHY_INTF_RGMII	/;"	d	file:
PHY_INTF_RMII	dwmac-mediatek.c	/^#define PHY_INTF_RMII	/;"	d	file:
PMT_NOT_SUPPORTED	common.h	/^#define PMT_NOT_SUPPORTED /;"	d
PMT_SUPPORTED	common.h	/^#define PMT_SUPPORTED /;"	d
POLL_DELAY_US	dwmac-intel.h	/^#define POLL_DELAY_US /;"	d
PPSCMDx	dwmac5.h	/^#define PPSCMDx(/;"	d
PPSEN0	dwmac5.h	/^#define PPSEN0	/;"	d
PPS_MAXIDX	dwmac5.h	/^#define PPS_MAXIDX(/;"	d
PPS_MINIDX	dwmac5.h	/^#define PPS_MINIDX(/;"	d
PPSx_MASK	dwmac5.h	/^#define PPSx_MASK(/;"	d
PRG_ETH0	dwmac-meson8b.c	/^#define PRG_ETH0	/;"	d	file:
PRG_ETH0_ADJ_DELAY	dwmac-meson8b.c	/^#define PRG_ETH0_ADJ_DELAY	/;"	d	file:
PRG_ETH0_ADJ_ENABLE	dwmac-meson8b.c	/^#define PRG_ETH0_ADJ_ENABLE	/;"	d	file:
PRG_ETH0_ADJ_SETUP	dwmac-meson8b.c	/^#define PRG_ETH0_ADJ_SETUP	/;"	d	file:
PRG_ETH0_ADJ_SKEW	dwmac-meson8b.c	/^#define PRG_ETH0_ADJ_SKEW	/;"	d	file:
PRG_ETH0_CLK_M250_DIV_SHIFT	dwmac-meson8b.c	/^#define PRG_ETH0_CLK_M250_DIV_SHIFT	/;"	d	file:
PRG_ETH0_CLK_M250_DIV_WIDTH	dwmac-meson8b.c	/^#define PRG_ETH0_CLK_M250_DIV_WIDTH	/;"	d	file:
PRG_ETH0_CLK_M250_SEL_MASK	dwmac-meson8b.c	/^#define PRG_ETH0_CLK_M250_SEL_MASK	/;"	d	file:
PRG_ETH0_EXT_PHY_MODE_MASK	dwmac-meson8b.c	/^#define PRG_ETH0_EXT_PHY_MODE_MASK	/;"	d	file:
PRG_ETH0_EXT_RGMII_MODE	dwmac-meson8b.c	/^#define PRG_ETH0_EXT_RGMII_MODE	/;"	d	file:
PRG_ETH0_EXT_RMII_MODE	dwmac-meson8b.c	/^#define PRG_ETH0_EXT_RMII_MODE	/;"	d	file:
PRG_ETH0_INVERTED_RMII_CLK	dwmac-meson8b.c	/^#define PRG_ETH0_INVERTED_RMII_CLK	/;"	d	file:
PRG_ETH0_RGMII_MODE	dwmac-meson8b.c	/^#define PRG_ETH0_RGMII_MODE	/;"	d	file:
PRG_ETH0_RGMII_TX_CLK_EN	dwmac-meson8b.c	/^#define PRG_ETH0_RGMII_TX_CLK_EN	/;"	d	file:
PRG_ETH0_TXDLY_MASK	dwmac-meson8b.c	/^#define PRG_ETH0_TXDLY_MASK	/;"	d	file:
PRG_ETH0_TX_AND_PHY_REF_CLK	dwmac-meson8b.c	/^#define PRG_ETH0_TX_AND_PHY_REF_CLK	/;"	d	file:
PRTYEN	dwmac5.h	/^#define PRTYEN	/;"	d
PTOV	dwmac5.h	/^#define PTOV	/;"	d
PTOV_SHIFT	dwmac5.h	/^#define PTOV_SHIFT	/;"	d
PTP_BINARY_ROLLOVER_MODE	stmmac_ptp.h	/^#define	PTP_BINARY_ROLLOVER_MODE	/;"	d
PTP_DIGITAL_ROLLOVER_MODE	stmmac_ptp.h	/^#define	PTP_DIGITAL_ROLLOVER_MODE	/;"	d
PTP_GMAC3_X_OFFSET	stmmac_ptp.h	/^#define	PTP_GMAC3_X_OFFSET	/;"	d
PTP_GMAC4_OFFSET	stmmac_ptp.h	/^#define	PTP_GMAC4_OFFSET	/;"	d
PTP_SSIR	stmmac_ptp.h	/^#define	PTP_SSIR	/;"	d
PTP_SSIR_SSINC_MASK	stmmac_ptp.h	/^#define	PTP_SSIR_SSINC_MASK	/;"	d
PTP_STNSR	stmmac_ptp.h	/^#define	PTP_STNSR	/;"	d
PTP_STNSUR	stmmac_ptp.h	/^#define	PTP_STNSUR	/;"	d
PTP_STNSUR_ADDSUB_SHIFT	stmmac_ptp.h	/^#define	PTP_STNSUR_ADDSUB_SHIFT	/;"	d
PTP_STSR	stmmac_ptp.h	/^#define	PTP_STSR	/;"	d
PTP_STSUR	stmmac_ptp.h	/^#define	PTP_STSUR	/;"	d
PTP_TAR	stmmac_ptp.h	/^#define	PTP_TAR	/;"	d
PTP_TCR	stmmac_ptp.h	/^#define	PTP_TCR	/;"	d
PTP_TCR_SNAPTYPSEL_1	stmmac_ptp.h	/^#define	PTP_TCR_SNAPTYPSEL_1	/;"	d
PTP_TCR_TSADDREG	stmmac_ptp.h	/^#define	PTP_TCR_TSADDREG	/;"	d
PTP_TCR_TSCFUPDT	stmmac_ptp.h	/^#define	PTP_TCR_TSCFUPDT	/;"	d
PTP_TCR_TSCTRLSSR	stmmac_ptp.h	/^#define	PTP_TCR_TSCTRLSSR	/;"	d
PTP_TCR_TSENA	stmmac_ptp.h	/^#define	PTP_TCR_TSENA	/;"	d
PTP_TCR_TSENALL	stmmac_ptp.h	/^#define	PTP_TCR_TSENALL	/;"	d
PTP_TCR_TSENMACADDR	stmmac_ptp.h	/^#define	PTP_TCR_TSENMACADDR	/;"	d
PTP_TCR_TSEVNTENA	stmmac_ptp.h	/^#define	PTP_TCR_TSEVNTENA	/;"	d
PTP_TCR_TSINIT	stmmac_ptp.h	/^#define	PTP_TCR_TSINIT	/;"	d
PTP_TCR_TSIPENA	stmmac_ptp.h	/^#define	PTP_TCR_TSIPENA	/;"	d
PTP_TCR_TSIPV4ENA	stmmac_ptp.h	/^#define	PTP_TCR_TSIPV4ENA	/;"	d
PTP_TCR_TSIPV6ENA	stmmac_ptp.h	/^#define	PTP_TCR_TSIPV6ENA	/;"	d
PTP_TCR_TSMSTRENA	stmmac_ptp.h	/^#define	PTP_TCR_TSMSTRENA	/;"	d
PTP_TCR_TSTRIG	stmmac_ptp.h	/^#define	PTP_TCR_TSTRIG	/;"	d
PTP_TCR_TSUPDT	stmmac_ptp.h	/^#define	PTP_TCR_TSUPDT	/;"	d
PTP_TCR_TSVER2ENA	stmmac_ptp.h	/^#define	PTP_TCR_TSVER2ENA	/;"	d
PTP_XGMAC_OFFSET	stmmac_ptp.h	/^#define PTP_XGMAC_OFFSET	/;"	d
PX30_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define PX30_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
PX30_GMAC_SPEED_100M	dwmac-rk.c	/^#define PX30_GMAC_SPEED_100M	/;"	d	file:
PX30_GMAC_SPEED_10M	dwmac-rk.c	/^#define PX30_GMAC_SPEED_10M	/;"	d	file:
PX30_GRF_GMAC_CON1	dwmac-rk.c	/^#define PX30_GRF_GMAC_CON1	/;"	d	file:
QSGMII_PCS_CAL_LCKDT_CTL	dwmac-ipq806x.c	/^#define QSGMII_PCS_CAL_LCKDT_CTL	/;"	d	file:
QSGMII_PCS_CAL_LCKDT_CTL_RST	dwmac-ipq806x.c	/^#define QSGMII_PCS_CAL_LCKDT_CTL_RST	/;"	d	file:
QSGMII_PHY_CDR_EN	dwmac-ipq806x.c	/^#define QSGMII_PHY_CDR_EN	/;"	d	file:
QSGMII_PHY_CDR_PI_SLEW_OFFSET	dwmac-ipq806x.c	/^#define QSGMII_PHY_CDR_PI_SLEW_OFFSET	/;"	d	file:
QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET	dwmac-ipq806x.c	/^#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET	/;"	d	file:
QSGMII_PHY_QSGMII_EN	dwmac-ipq806x.c	/^#define QSGMII_PHY_QSGMII_EN	/;"	d	file:
QSGMII_PHY_RX_DC_BIAS_OFFSET	dwmac-ipq806x.c	/^#define QSGMII_PHY_RX_DC_BIAS_OFFSET	/;"	d	file:
QSGMII_PHY_RX_FRONT_EN	dwmac-ipq806x.c	/^#define QSGMII_PHY_RX_FRONT_EN	/;"	d	file:
QSGMII_PHY_RX_INPUT_EQU_OFFSET	dwmac-ipq806x.c	/^#define QSGMII_PHY_RX_INPUT_EQU_OFFSET	/;"	d	file:
QSGMII_PHY_RX_SIGNAL_DETECT_EN	dwmac-ipq806x.c	/^#define QSGMII_PHY_RX_SIGNAL_DETECT_EN	/;"	d	file:
QSGMII_PHY_SGMII_CTL	dwmac-ipq806x.c	/^#define QSGMII_PHY_SGMII_CTL(/;"	d	file:
QSGMII_PHY_TX_DRIVER_EN	dwmac-ipq806x.c	/^#define QSGMII_PHY_TX_DRIVER_EN	/;"	d	file:
QSGMII_PHY_TX_DRV_AMP_OFFSET	dwmac-ipq806x.c	/^#define QSGMII_PHY_TX_DRV_AMP_OFFSET	/;"	d	file:
RDES0_COLLISION	descs.h	/^#define	RDES0_COLLISION	/;"	d
RDES0_CRC_ERROR	descs.h	/^#define	RDES0_CRC_ERROR	/;"	d
RDES0_DA_FILTER_FAIL	descs.h	/^#define	RDES0_DA_FILTER_FAIL	/;"	d
RDES0_DESCRIPTOR_ERROR	descs.h	/^#define	RDES0_DESCRIPTOR_ERROR	/;"	d
RDES0_DRIBBLING	descs.h	/^#define	RDES0_DRIBBLING	/;"	d
RDES0_ERROR_SUMMARY	descs.h	/^#define	RDES0_ERROR_SUMMARY	/;"	d
RDES0_FIRST_DESCRIPTOR	descs.h	/^#define	RDES0_FIRST_DESCRIPTOR	/;"	d
RDES0_FRAME_LEN_MASK	descs.h	/^#define	RDES0_FRAME_LEN_MASK	/;"	d
RDES0_FRAME_LEN_SHIFT	descs.h	/^#define RDES0_FRAME_LEN_SHIFT	/;"	d
RDES0_FRAME_TYPE	descs.h	/^#define	RDES0_FRAME_TYPE	/;"	d
RDES0_IPC_CSUM_ERROR	descs.h	/^#define	RDES0_IPC_CSUM_ERROR	/;"	d
RDES0_LAST_DESCRIPTOR	descs.h	/^#define	RDES0_LAST_DESCRIPTOR	/;"	d
RDES0_LENGTH_ERROR	descs.h	/^#define	RDES0_LENGTH_ERROR	/;"	d
RDES0_MII_ERROR	descs.h	/^#define	RDES0_MII_ERROR	/;"	d
RDES0_OVERFLOW_ERROR	descs.h	/^#define	RDES0_OVERFLOW_ERROR	/;"	d
RDES0_OWN	descs.h	/^#define	RDES0_OWN	/;"	d
RDES0_PAYLOAD_CSUM_ERR	descs.h	/^#define	RDES0_PAYLOAD_CSUM_ERR	/;"	d
RDES0_RECEIVE_WATCHDOG	descs.h	/^#define	RDES0_RECEIVE_WATCHDOG	/;"	d
RDES0_SA_FILTER_FAIL	descs.h	/^#define	RDES0_SA_FILTER_FAIL	/;"	d
RDES0_VLAN_TAG	descs.h	/^#define	RDES0_VLAN_TAG	/;"	d
RDES0_VLAN_TAG_MASK	dwmac4_descs.h	/^#define RDES0_VLAN_TAG_MASK	/;"	d
RDES1_BUFFER1_SIZE_MASK	descs.h	/^#define	RDES1_BUFFER1_SIZE_MASK	/;"	d
RDES1_BUFFER2_SIZE_MASK	descs.h	/^#define	RDES1_BUFFER2_SIZE_MASK	/;"	d
RDES1_BUFFER2_SIZE_SHIFT	descs.h	/^#define	RDES1_BUFFER2_SIZE_SHIFT	/;"	d
RDES1_DISABLE_IC	descs.h	/^#define	RDES1_DISABLE_IC	/;"	d
RDES1_END_RING	descs.h	/^#define	RDES1_END_RING	/;"	d
RDES1_IPV4_HEADER	dwmac4_descs.h	/^#define RDES1_IPV4_HEADER	/;"	d
RDES1_IPV6_HEADER	dwmac4_descs.h	/^#define RDES1_IPV6_HEADER	/;"	d
RDES1_IP_CSUM_BYPASSED	dwmac4_descs.h	/^#define RDES1_IP_CSUM_BYPASSED	/;"	d
RDES1_IP_CSUM_ERROR	dwmac4_descs.h	/^#define RDES1_IP_CSUM_ERROR	/;"	d
RDES1_IP_HDR_ERROR	dwmac4_descs.h	/^#define RDES1_IP_HDR_ERROR	/;"	d
RDES1_IP_PAYLOAD_TYPE_MASK	dwmac4_descs.h	/^#define RDES1_IP_PAYLOAD_TYPE_MASK	/;"	d
RDES1_IP_TYPE1_CSUM_MASK	dwmac4_descs.h	/^#define RDES1_IP_TYPE1_CSUM_MASK	/;"	d
RDES1_PTP_MSG_TYPE_MASK	dwmac4_descs.h	/^#define RDES1_PTP_MSG_TYPE_MASK	/;"	d
RDES1_PTP_PACKET_TYPE	dwmac4_descs.h	/^#define RDES1_PTP_PACKET_TYPE	/;"	d
RDES1_PTP_VER	dwmac4_descs.h	/^#define RDES1_PTP_VER	/;"	d
RDES1_SECOND_ADDRESS_CHAINED	descs.h	/^#define	RDES1_SECOND_ADDRESS_CHAINED	/;"	d
RDES1_TIMESTAMP_AVAILABLE	dwmac4_descs.h	/^#define RDES1_TIMESTAMP_AVAILABLE	/;"	d
RDES1_TIMESTAMP_AVAILABLE_SHIFT	dwmac4_descs.h	/^#define RDES1_TIMESTAMP_AVAILABLE_SHIFT	/;"	d
RDES1_TIMESTAMP_DROPPED	dwmac4_descs.h	/^#define RDES1_TIMESTAMP_DROPPED	/;"	d
RDES2_DA_FILTER_FAIL	dwmac4_descs.h	/^#define RDES2_DA_FILTER_FAIL	/;"	d
RDES2_HASH_FILTER_STATUS	dwmac4_descs.h	/^#define RDES2_HASH_FILTER_STATUS	/;"	d
RDES2_HASH_VALUE_MATCH_MASK	dwmac4_descs.h	/^#define RDES2_HASH_VALUE_MATCH_MASK	/;"	d
RDES2_HL	dwmac4_descs.h	/^#define RDES2_HL	/;"	d
RDES2_L3_FILTER_MATCH	dwmac4_descs.h	/^#define RDES2_L3_FILTER_MATCH	/;"	d
RDES2_L3_L4_FILT_NB_MATCH_MASK	dwmac4_descs.h	/^#define RDES2_L3_L4_FILT_NB_MATCH_MASK	/;"	d
RDES2_L3_L4_FILT_NB_MATCH_SHIFT	dwmac4_descs.h	/^#define RDES2_L3_L4_FILT_NB_MATCH_SHIFT	/;"	d
RDES2_L3_L4_HEADER_SIZE_MASK	dwmac4_descs.h	/^#define RDES2_L3_L4_HEADER_SIZE_MASK	/;"	d
RDES2_L4_FILTER_MATCH	dwmac4_descs.h	/^#define RDES2_L4_FILTER_MATCH	/;"	d
RDES2_MAC_ADDR_MATCH_MASK	dwmac4_descs.h	/^#define RDES2_MAC_ADDR_MATCH_MASK	/;"	d
RDES2_SA_FILTER_FAIL	dwmac4_descs.h	/^#define RDES2_SA_FILTER_FAIL	/;"	d
RDES2_VLAN_FILTER_STATUS	dwmac4_descs.h	/^#define RDES2_VLAN_FILTER_STATUS	/;"	d
RDES3_BUFFER1_VALID_ADDR	dwmac4_descs.h	/^#define RDES3_BUFFER1_VALID_ADDR	/;"	d
RDES3_BUFFER2_VALID_ADDR	dwmac4_descs.h	/^#define RDES3_BUFFER2_VALID_ADDR	/;"	d
RDES3_CONTEXT_DESCRIPTOR	dwmac4_descs.h	/^#define RDES3_CONTEXT_DESCRIPTOR	/;"	d
RDES3_CONTEXT_DESCRIPTOR_SHIFT	dwmac4_descs.h	/^#define RDES3_CONTEXT_DESCRIPTOR_SHIFT	/;"	d
RDES3_CRC_ERROR	dwmac4_descs.h	/^#define RDES3_CRC_ERROR	/;"	d
RDES3_DRIBBLE_ERROR	dwmac4_descs.h	/^#define RDES3_DRIBBLE_ERROR	/;"	d
RDES3_ERROR_SUMMARY	dwmac4_descs.h	/^#define RDES3_ERROR_SUMMARY	/;"	d
RDES3_FIRST_DESCRIPTOR	dwmac4_descs.h	/^#define RDES3_FIRST_DESCRIPTOR	/;"	d
RDES3_GIANT_PACKET	dwmac4_descs.h	/^#define RDES3_GIANT_PACKET	/;"	d
RDES3_INT_ON_COMPLETION_EN	dwmac4_descs.h	/^#define RDES3_INT_ON_COMPLETION_EN	/;"	d
RDES3_LAST_DESCRIPTOR	dwmac4_descs.h	/^#define RDES3_LAST_DESCRIPTOR	/;"	d
RDES3_OVERFLOW_ERROR	dwmac4_descs.h	/^#define RDES3_OVERFLOW_ERROR	/;"	d
RDES3_OWN	dwmac4_descs.h	/^#define RDES3_OWN	/;"	d
RDES3_PACKET_LEN_TYPE_MASK	dwmac4_descs.h	/^#define RDES3_PACKET_LEN_TYPE_MASK	/;"	d
RDES3_PACKET_SIZE_MASK	dwmac4_descs.h	/^#define RDES3_PACKET_SIZE_MASK	/;"	d
RDES3_RDES0_VALID	dwmac4_descs.h	/^#define RDES3_RDES0_VALID	/;"	d
RDES3_RDES1_VALID	dwmac4_descs.h	/^#define RDES3_RDES1_VALID	/;"	d
RDES3_RDES2_VALID	dwmac4_descs.h	/^#define RDES3_RDES2_VALID	/;"	d
RDES3_RECEIVE_ERROR	dwmac4_descs.h	/^#define RDES3_RECEIVE_ERROR	/;"	d
RDES3_RECEIVE_WATCHDOG	dwmac4_descs.h	/^#define RDES3_RECEIVE_WATCHDOG	/;"	d
RDES_EXT_DELAY_REQ	descs.h	/^#define RDES_EXT_DELAY_REQ	/;"	d
RDES_EXT_DELAY_RESP	descs.h	/^#define RDES_EXT_DELAY_RESP	/;"	d
RDES_EXT_FOLLOW_UP	descs.h	/^#define RDES_EXT_FOLLOW_UP	/;"	d
RDES_EXT_NO_PTP	descs.h	/^#define RDES_EXT_NO_PTP	/;"	d
RDES_EXT_PDELAY_FOLLOW_UP	descs.h	/^#define RDES_EXT_PDELAY_FOLLOW_UP	/;"	d
RDES_EXT_PDELAY_REQ	descs.h	/^#define RDES_EXT_PDELAY_REQ	/;"	d
RDES_EXT_PDELAY_RESP	descs.h	/^#define RDES_EXT_PDELAY_RESP	/;"	d
RDES_EXT_SYNC	descs.h	/^#define RDES_EXT_SYNC	/;"	d
RDES_PTP_ANNOUNCE	descs.h	/^#define RDES_PTP_ANNOUNCE	/;"	d
RDES_PTP_MANAGEMENT	descs.h	/^#define RDES_PTP_MANAGEMENT	/;"	d
RDES_PTP_PKT_RESERVED_TYPE	descs.h	/^#define RDES_PTP_PKT_RESERVED_TYPE	/;"	d
RDES_PTP_SIGNALING	descs.h	/^#define RDES_PTP_SIGNALING	/;"	d
REG_SPACE_SIZE	stmmac_ethtool.c	/^#define REG_SPACE_SIZE	/;"	d	file:
REMAKE_INITRD	dkms.conf	/^REMAKE_INITRD="YES"$/;"	k
RFA_FULL_MINUS_1K	dwmac1000.h	/^#define RFA_FULL_MINUS_1K	/;"	d
RFA_FULL_MINUS_2K	dwmac1000.h	/^#define RFA_FULL_MINUS_2K	/;"	d
RFA_FULL_MINUS_3K	dwmac1000.h	/^#define RFA_FULL_MINUS_3K	/;"	d
RFA_FULL_MINUS_4K	dwmac1000.h	/^#define RFA_FULL_MINUS_4K	/;"	d
RFA_FULL_MINUS_5K	dwmac1000.h	/^#define RFA_FULL_MINUS_5K	/;"	d
RFA_FULL_MINUS_6K	dwmac1000.h	/^#define RFA_FULL_MINUS_6K	/;"	d
RFA_FULL_MINUS_7K	dwmac1000.h	/^#define RFA_FULL_MINUS_7K	/;"	d
RFD_FULL_MINUS_1K	dwmac1000.h	/^#define RFD_FULL_MINUS_1K	/;"	d
RFD_FULL_MINUS_2K	dwmac1000.h	/^#define RFD_FULL_MINUS_2K	/;"	d
RFD_FULL_MINUS_3K	dwmac1000.h	/^#define RFD_FULL_MINUS_3K	/;"	d
RFD_FULL_MINUS_4K	dwmac1000.h	/^#define RFD_FULL_MINUS_4K	/;"	d
RFD_FULL_MINUS_5K	dwmac1000.h	/^#define RFD_FULL_MINUS_5K	/;"	d
RFD_FULL_MINUS_6K	dwmac1000.h	/^#define RFD_FULL_MINUS_6K	/;"	d
RFD_FULL_MINUS_7K	dwmac1000.h	/^#define RFD_FULL_MINUS_7K	/;"	d
RGMII_1000_NOM_CLK_FREQ	dwmac-qcom-ethqos.c	/^#define RGMII_1000_NOM_CLK_FREQ	/;"	d	file:
RGMII_CONFIG2_CLK_DIVIDE_SEL	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_CLK_DIVIDE_SEL	/;"	d	file:
RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	/;"	d	file:
RGMII_CONFIG2_RGMII_CLK_SEL_CFG	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG	/;"	d	file:
RGMII_CONFIG2_RSVD_CONFIG15	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_RSVD_CONFIG15	/;"	d	file:
RGMII_CONFIG2_RX_PROG_SWAP	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_RX_PROG_SWAP	/;"	d	file:
RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	/;"	d	file:
RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN	/;"	d	file:
RGMII_CONFIG_BYPASS_TX_ID_EN	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_BYPASS_TX_ID_EN	/;"	d	file:
RGMII_CONFIG_DDR_MODE	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_DDR_MODE	/;"	d	file:
RGMII_CONFIG_FUNC_CLK_EN	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_FUNC_CLK_EN	/;"	d	file:
RGMII_CONFIG_GPIO_CFG_RX_INT	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_GPIO_CFG_RX_INT	/;"	d	file:
RGMII_CONFIG_GPIO_CFG_TX_INT	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_GPIO_CFG_TX_INT	/;"	d	file:
RGMII_CONFIG_INTF_SEL	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_INTF_SEL	/;"	d	file:
RGMII_CONFIG_LOOPBACK_EN	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_LOOPBACK_EN	/;"	d	file:
RGMII_CONFIG_MAX_SPD_PRG_2	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_MAX_SPD_PRG_2	/;"	d	file:
RGMII_CONFIG_MAX_SPD_PRG_9	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_MAX_SPD_PRG_9	/;"	d	file:
RGMII_CONFIG_POS_NEG_DATA_SEL	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_POS_NEG_DATA_SEL	/;"	d	file:
RGMII_CONFIG_PROG_SWAP	dwmac-qcom-ethqos.c	/^#define RGMII_CONFIG_PROG_SWAP	/;"	d	file:
RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ	dwmac-qcom-ethqos.c	/^#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ	/;"	d	file:
RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ	dwmac-qcom-ethqos.c	/^#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ	/;"	d	file:
RGMII_IO_MACRO_CONFIG	dwmac-qcom-ethqos.c	/^#define RGMII_IO_MACRO_CONFIG	/;"	d	file:
RGMII_IO_MACRO_CONFIG2	dwmac-qcom-ethqos.c	/^#define RGMII_IO_MACRO_CONFIG2	/;"	d	file:
RGMII_IO_MACRO_DEBUG1	dwmac-qcom-ethqos.c	/^#define RGMII_IO_MACRO_DEBUG1	/;"	d	file:
RK3128_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3128_GMAC_CLK_125M /;"	d	file:
RK3128_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3128_GMAC_CLK_25M /;"	d	file:
RK3128_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3128_GMAC_CLK_2_5M /;"	d	file:
RK3128_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3128_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3128_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3128_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3128_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3128_GMAC_FLOW_CTRL /;"	d	file:
RK3128_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3128_GMAC_FLOW_CTRL_CLR /;"	d	file:
RK3128_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3128_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3128_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3128_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3128_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3128_GMAC_RMII_CLK_25M /;"	d	file:
RK3128_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3128_GMAC_RMII_CLK_2_5M /;"	d	file:
RK3128_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3128_GMAC_RMII_MODE /;"	d	file:
RK3128_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3128_GMAC_RMII_MODE_CLR /;"	d	file:
RK3128_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3128_GMAC_RXCLK_DLY_DISABLE /;"	d	file:
RK3128_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3128_GMAC_RXCLK_DLY_ENABLE /;"	d	file:
RK3128_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3128_GMAC_SPEED_100M /;"	d	file:
RK3128_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3128_GMAC_SPEED_10M /;"	d	file:
RK3128_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3128_GMAC_TXCLK_DLY_DISABLE /;"	d	file:
RK3128_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3128_GMAC_TXCLK_DLY_ENABLE /;"	d	file:
RK3128_GRF_MAC_CON0	dwmac-rk.c	/^#define RK3128_GRF_MAC_CON0	/;"	d	file:
RK3128_GRF_MAC_CON1	dwmac-rk.c	/^#define RK3128_GRF_MAC_CON1	/;"	d	file:
RK3228_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3228_GMAC_CLK_125M	/;"	d	file:
RK3228_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3228_GMAC_CLK_25M	/;"	d	file:
RK3228_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3228_GMAC_CLK_2_5M	/;"	d	file:
RK3228_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3228_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3228_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3228_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3228_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3228_GMAC_FLOW_CTRL	/;"	d	file:
RK3228_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3228_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3228_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3228_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3228_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3228_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3228_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3228_GMAC_RMII_CLK_25M	/;"	d	file:
RK3228_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3228_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3228_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3228_GMAC_RMII_MODE	/;"	d	file:
RK3228_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3228_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3228_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3228_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3228_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3228_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3228_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3228_GMAC_SPEED_100M	/;"	d	file:
RK3228_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3228_GMAC_SPEED_10M	/;"	d	file:
RK3228_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3228_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3228_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3228_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3228_GRF_CON_MUX	dwmac-rk.c	/^#define RK3228_GRF_CON_MUX	/;"	d	file:
RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY	dwmac-rk.c	/^#define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY	/;"	d	file:
RK3228_GRF_MAC_CON0	dwmac-rk.c	/^#define RK3228_GRF_MAC_CON0	/;"	d	file:
RK3228_GRF_MAC_CON1	dwmac-rk.c	/^#define RK3228_GRF_MAC_CON1	/;"	d	file:
RK3288_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3288_GMAC_CLK_125M	/;"	d	file:
RK3288_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3288_GMAC_CLK_25M	/;"	d	file:
RK3288_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3288_GMAC_CLK_2_5M	/;"	d	file:
RK3288_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3288_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3288_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3288_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3288_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3288_GMAC_FLOW_CTRL	/;"	d	file:
RK3288_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3288_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3288_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3288_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3288_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3288_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3288_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3288_GMAC_RMII_CLK_25M	/;"	d	file:
RK3288_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3288_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3288_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3288_GMAC_RMII_MODE	/;"	d	file:
RK3288_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3288_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3288_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3288_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3288_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3288_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3288_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3288_GMAC_SPEED_100M	/;"	d	file:
RK3288_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3288_GMAC_SPEED_10M	/;"	d	file:
RK3288_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3288_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3288_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3288_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3288_GRF_SOC_CON1	dwmac-rk.c	/^#define RK3288_GRF_SOC_CON1	/;"	d	file:
RK3288_GRF_SOC_CON3	dwmac-rk.c	/^#define RK3288_GRF_SOC_CON3	/;"	d	file:
RK3328_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3328_GMAC_CLK_125M	/;"	d	file:
RK3328_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3328_GMAC_CLK_25M	/;"	d	file:
RK3328_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3328_GMAC_CLK_2_5M	/;"	d	file:
RK3328_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3328_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3328_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3328_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3328_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3328_GMAC_FLOW_CTRL	/;"	d	file:
RK3328_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3328_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3328_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3328_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3328_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3328_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3328_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3328_GMAC_RMII_CLK_25M	/;"	d	file:
RK3328_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3328_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3328_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3328_GMAC_RMII_MODE	/;"	d	file:
RK3328_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3328_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3328_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3328_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3328_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3328_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3328_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3328_GMAC_SPEED_100M	/;"	d	file:
RK3328_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3328_GMAC_SPEED_10M	/;"	d	file:
RK3328_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3328_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3328_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3328_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3328_GRF_MACPHY_CON1	dwmac-rk.c	/^#define RK3328_GRF_MACPHY_CON1	/;"	d	file:
RK3328_GRF_MAC_CON0	dwmac-rk.c	/^#define RK3328_GRF_MAC_CON0	/;"	d	file:
RK3328_GRF_MAC_CON1	dwmac-rk.c	/^#define RK3328_GRF_MAC_CON1	/;"	d	file:
RK3328_GRF_MAC_CON2	dwmac-rk.c	/^#define RK3328_GRF_MAC_CON2	/;"	d	file:
RK3328_MACPHY_RMII_MODE	dwmac-rk.c	/^#define RK3328_MACPHY_RMII_MODE	/;"	d	file:
RK3366_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3366_GMAC_CLK_125M	/;"	d	file:
RK3366_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3366_GMAC_CLK_25M	/;"	d	file:
RK3366_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3366_GMAC_CLK_2_5M	/;"	d	file:
RK3366_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3366_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3366_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3366_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3366_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3366_GMAC_FLOW_CTRL	/;"	d	file:
RK3366_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3366_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3366_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3366_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3366_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3366_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3366_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3366_GMAC_RMII_CLK_25M	/;"	d	file:
RK3366_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3366_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3366_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3366_GMAC_RMII_MODE	/;"	d	file:
RK3366_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3366_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3366_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3366_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3366_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3366_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3366_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3366_GMAC_SPEED_100M	/;"	d	file:
RK3366_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3366_GMAC_SPEED_10M	/;"	d	file:
RK3366_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3366_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3366_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3366_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3366_GRF_SOC_CON6	dwmac-rk.c	/^#define RK3366_GRF_SOC_CON6	/;"	d	file:
RK3366_GRF_SOC_CON7	dwmac-rk.c	/^#define RK3366_GRF_SOC_CON7	/;"	d	file:
RK3368_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3368_GMAC_CLK_125M	/;"	d	file:
RK3368_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3368_GMAC_CLK_25M	/;"	d	file:
RK3368_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3368_GMAC_CLK_2_5M	/;"	d	file:
RK3368_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3368_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3368_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3368_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3368_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3368_GMAC_FLOW_CTRL	/;"	d	file:
RK3368_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3368_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3368_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3368_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3368_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3368_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3368_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3368_GMAC_RMII_CLK_25M	/;"	d	file:
RK3368_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3368_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3368_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3368_GMAC_RMII_MODE	/;"	d	file:
RK3368_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3368_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3368_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3368_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3368_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3368_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3368_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3368_GMAC_SPEED_100M	/;"	d	file:
RK3368_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3368_GMAC_SPEED_10M	/;"	d	file:
RK3368_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3368_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3368_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3368_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3368_GRF_SOC_CON15	dwmac-rk.c	/^#define RK3368_GRF_SOC_CON15	/;"	d	file:
RK3368_GRF_SOC_CON16	dwmac-rk.c	/^#define RK3368_GRF_SOC_CON16	/;"	d	file:
RK3399_GMAC_CLK_125M	dwmac-rk.c	/^#define RK3399_GMAC_CLK_125M	/;"	d	file:
RK3399_GMAC_CLK_25M	dwmac-rk.c	/^#define RK3399_GMAC_CLK_25M	/;"	d	file:
RK3399_GMAC_CLK_2_5M	dwmac-rk.c	/^#define RK3399_GMAC_CLK_2_5M	/;"	d	file:
RK3399_GMAC_CLK_RX_DL_CFG	dwmac-rk.c	/^#define RK3399_GMAC_CLK_RX_DL_CFG(/;"	d	file:
RK3399_GMAC_CLK_TX_DL_CFG	dwmac-rk.c	/^#define RK3399_GMAC_CLK_TX_DL_CFG(/;"	d	file:
RK3399_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RK3399_GMAC_FLOW_CTRL	/;"	d	file:
RK3399_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RK3399_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RK3399_GMAC_PHY_INTF_SEL_RGMII	dwmac-rk.c	/^#define RK3399_GMAC_PHY_INTF_SEL_RGMII	/;"	d	file:
RK3399_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RK3399_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RK3399_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RK3399_GMAC_RMII_CLK_25M	/;"	d	file:
RK3399_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RK3399_GMAC_RMII_CLK_2_5M	/;"	d	file:
RK3399_GMAC_RMII_MODE	dwmac-rk.c	/^#define RK3399_GMAC_RMII_MODE	/;"	d	file:
RK3399_GMAC_RMII_MODE_CLR	dwmac-rk.c	/^#define RK3399_GMAC_RMII_MODE_CLR	/;"	d	file:
RK3399_GMAC_RXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3399_GMAC_RXCLK_DLY_DISABLE	/;"	d	file:
RK3399_GMAC_RXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3399_GMAC_RXCLK_DLY_ENABLE	/;"	d	file:
RK3399_GMAC_SPEED_100M	dwmac-rk.c	/^#define RK3399_GMAC_SPEED_100M	/;"	d	file:
RK3399_GMAC_SPEED_10M	dwmac-rk.c	/^#define RK3399_GMAC_SPEED_10M	/;"	d	file:
RK3399_GMAC_TXCLK_DLY_DISABLE	dwmac-rk.c	/^#define RK3399_GMAC_TXCLK_DLY_DISABLE	/;"	d	file:
RK3399_GMAC_TXCLK_DLY_ENABLE	dwmac-rk.c	/^#define RK3399_GMAC_TXCLK_DLY_ENABLE	/;"	d	file:
RK3399_GRF_SOC_CON5	dwmac-rk.c	/^#define RK3399_GRF_SOC_CON5	/;"	d	file:
RK3399_GRF_SOC_CON6	dwmac-rk.c	/^#define RK3399_GRF_SOC_CON6	/;"	d	file:
RK_GMAC2PHY_RMII_MODE	dwmac-rk.c	/^#define RK_GMAC2PHY_RMII_MODE	/;"	d	file:
RK_GRF_CON2_MACPHY_ID	dwmac-rk.c	/^#define RK_GRF_CON2_MACPHY_ID	/;"	d	file:
RK_GRF_CON3_MACPHY_ID	dwmac-rk.c	/^#define RK_GRF_CON3_MACPHY_ID	/;"	d	file:
RK_GRF_MACPHY_CON0	dwmac-rk.c	/^#define RK_GRF_MACPHY_CON0	/;"	d	file:
RK_GRF_MACPHY_CON1	dwmac-rk.c	/^#define RK_GRF_MACPHY_CON1	/;"	d	file:
RK_GRF_MACPHY_CON2	dwmac-rk.c	/^#define RK_GRF_MACPHY_CON2	/;"	d	file:
RK_GRF_MACPHY_CON3	dwmac-rk.c	/^#define RK_GRF_MACPHY_CON3	/;"	d	file:
RK_MACPHY_CFG_CLK_50M	dwmac-rk.c	/^#define RK_MACPHY_CFG_CLK_50M	/;"	d	file:
RK_MACPHY_DISABLE	dwmac-rk.c	/^#define RK_MACPHY_DISABLE	/;"	d	file:
RK_MACPHY_ENABLE	dwmac-rk.c	/^#define RK_MACPHY_ENABLE	/;"	d	file:
RMII_CLK_SRC_INTERNAL	dwmac-mediatek.c	/^#define RMII_CLK_SRC_INTERNAL	/;"	d	file:
RMII_CLK_SRC_RXC	dwmac-mediatek.c	/^#define RMII_CLK_SRC_RXC	/;"	d	file:
RPCEIE	dwmac5.h	/^#define RPCEIE	/;"	d
RV1108_GMAC_FLOW_CTRL	dwmac-rk.c	/^#define RV1108_GMAC_FLOW_CTRL	/;"	d	file:
RV1108_GMAC_FLOW_CTRL_CLR	dwmac-rk.c	/^#define RV1108_GMAC_FLOW_CTRL_CLR	/;"	d	file:
RV1108_GMAC_PHY_INTF_SEL_RMII	dwmac-rk.c	/^#define RV1108_GMAC_PHY_INTF_SEL_RMII	/;"	d	file:
RV1108_GMAC_RMII_CLK_25M	dwmac-rk.c	/^#define RV1108_GMAC_RMII_CLK_25M	/;"	d	file:
RV1108_GMAC_RMII_CLK_2_5M	dwmac-rk.c	/^#define RV1108_GMAC_RMII_CLK_2_5M	/;"	d	file:
RV1108_GMAC_SPEED_100M	dwmac-rk.c	/^#define RV1108_GMAC_SPEED_100M	/;"	d	file:
RV1108_GMAC_SPEED_10M	dwmac-rk.c	/^#define RV1108_GMAC_SPEED_10M	/;"	d	file:
RV1108_GRF_GMAC_CON0	dwmac-rk.c	/^#define RV1108_GRF_GMAC_CON0	/;"	d	file:
RXCEIE	dwmac5.h	/^#define RXCEIE	/;"	d
RXPEIEC	dwmac5.h	/^#define RXPEIEC	/;"	d
RXPEIEE	dwmac5.h	/^#define RXPEIEE	/;"	d
RXPI	dwmac5.h	/^#define RXPI	/;"	d
SDC4_STATUS	dwmac-qcom-ethqos.c	/^#define SDC4_STATUS	/;"	d	file:
SDC4_STATUS_DLL_LOCK	dwmac-qcom-ethqos.c	/^#define SDC4_STATUS_DLL_LOCK	/;"	d	file:
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	dwmac-qcom-ethqos.c	/^#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	/;"	d	file:
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	dwmac-qcom-ethqos.c	/^#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	/;"	d	file:
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN	/;"	d	file:
SDCC_DDR_CONFIG_PRG_DLY_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DDR_CONFIG_PRG_DLY_EN	/;"	d	file:
SDCC_DDR_CONFIG_PRG_RCLK_DLY	dwmac-qcom-ethqos.c	/^#define SDCC_DDR_CONFIG_PRG_RCLK_DLY	/;"	d	file:
SDCC_DLL_CDR_FINE_PHASE	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CDR_FINE_PHASE	/;"	d	file:
SDCC_DLL_CONFIG2_DDR_CAL_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG2_DDR_CAL_EN	/;"	d	file:
SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	/;"	d	file:
SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW	/;"	d	file:
SDCC_DLL_CONFIG2_DLL_CLOCK_DIS	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS	/;"	d	file:
SDCC_DLL_CONFIG2_MCLK_FREQ_CALC	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC	/;"	d	file:
SDCC_DLL_CONFIG_CDR_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_CDR_EN	/;"	d	file:
SDCC_DLL_CONFIG_CDR_EXT_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_CDR_EXT_EN	/;"	d	file:
SDCC_DLL_CONFIG_CDR_SELEXT	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_CDR_SELEXT	/;"	d	file:
SDCC_DLL_CONFIG_CK_OUT_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_CK_OUT_EN	/;"	d	file:
SDCC_DLL_CONFIG_DLL_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_DLL_EN	/;"	d	file:
SDCC_DLL_CONFIG_DLL_RST	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_DLL_RST	/;"	d	file:
SDCC_DLL_CONFIG_MCLK_FREQ	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_MCLK_FREQ	/;"	d	file:
SDCC_DLL_CONFIG_PDN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_CONFIG_PDN	/;"	d	file:
SDCC_DLL_MCLK_GATING_EN	dwmac-qcom-ethqos.c	/^#define SDCC_DLL_MCLK_GATING_EN	/;"	d	file:
SDCC_HC_REG_DDR_CONFIG	dwmac-qcom-ethqos.c	/^#define SDCC_HC_REG_DDR_CONFIG	/;"	d	file:
SDCC_HC_REG_DLL_CONFIG	dwmac-qcom-ethqos.c	/^#define SDCC_HC_REG_DLL_CONFIG	/;"	d	file:
SDCC_HC_REG_DLL_CONFIG2	dwmac-qcom-ethqos.c	/^#define SDCC_HC_REG_DLL_CONFIG2	/;"	d	file:
SDCC_USR_CTL	dwmac-qcom-ethqos.c	/^#define SDCC_USR_CTL	/;"	d	file:
SDMEMCOMPPADCTRL	dwmac-dwc-qos-eth.c	/^#define SDMEMCOMPPADCTRL /;"	d	file:
SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD	dwmac-dwc-qos-eth.c	/^#define  SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD /;"	d	file:
SERDES_GCR0	dwmac-intel.h	/^#define SERDES_GCR0	/;"	d
SERDES_GSR0	dwmac-intel.h	/^#define SERDES_GSR0	/;"	d
SERDES_PLL_CLK	dwmac-intel.h	/^#define SERDES_PLL_CLK	/;"	d
SERDES_PWR_ST_MASK	dwmac-intel.h	/^#define SERDES_PWR_ST_MASK	/;"	d
SERDES_PWR_ST_P0	dwmac-intel.h	/^#define SERDES_PWR_ST_P0	/;"	d
SERDES_PWR_ST_P3	dwmac-intel.h	/^#define SERDES_PWR_ST_P3	/;"	d
SERDES_PWR_ST_SHIFT	dwmac-intel.h	/^#define SERDES_PWR_ST_SHIFT	/;"	d
SERDES_RST	dwmac-intel.h	/^#define SERDES_RST	/;"	d
SF_DMA_MODE	common.h	/^#define SF_DMA_MODE /;"	d
SGMII_ADAPTER_CTRL_REG	altr_tse_pcs.c	/^#define SGMII_ADAPTER_CTRL_REG	/;"	d	file:
SGMII_ADAPTER_CTRL_REG	dwmac-socfpga.c	/^#define SGMII_ADAPTER_CTRL_REG /;"	d	file:
SGMII_ADAPTER_DISABLE	altr_tse_pcs.c	/^#define SGMII_ADAPTER_DISABLE	/;"	d	file:
SGMII_ADAPTER_DISABLE	dwmac-socfpga.c	/^#define SGMII_ADAPTER_DISABLE /;"	d	file:
SGMII_ADAPTER_ENABLE	altr_tse_pcs.c	/^#define SGMII_ADAPTER_ENABLE	/;"	d	file:
SRWO	dwmac5.h	/^#define SRWO	/;"	d
SSWL	dwmac5.h	/^#define SSWL	/;"	d
STARTBUSY	dwmac5.h	/^#define STARTBUSY	/;"	d
STAT_OFF	dwmac5.c	/^#define STAT_OFF(/;"	d	file:
STAT_OFF	dwxgmac2_core.c	/^#define STAT_OFF(/;"	d	file:
STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK	dwmac-sti.c	/^#define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK	/;"	d	file:
STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK	dwmac-sti.c	/^#define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK	/;"	d	file:
STID127_RETIME_SRC_MASK	dwmac-sti.c	/^#define STID127_RETIME_SRC_MASK	/;"	d	file:
STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK	dwmac-sti.c	/^#define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK	/;"	d	file:
STIH4XX_ETH_SEL_TXCLK_NOT_CLK125	dwmac-sti.c	/^#define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125	/;"	d	file:
STIH4XX_ETH_SEL_TX_RETIME_CLK	dwmac-sti.c	/^#define STIH4XX_ETH_SEL_TX_RETIME_CLK	/;"	d	file:
STIH4XX_RETIME_SRC_MASK	dwmac-sti.c	/^#define STIH4XX_RETIME_SRC_MASK	/;"	d	file:
STMMAC_ALIGN	stmmac_main.c	/^#define	STMMAC_ALIGN(/;"	d	file:
STMMAC_CHAIN_MODE	common.h	/^#define STMMAC_CHAIN_MODE	/;"	d
STMMAC_CHAN0	common.h	/^#define STMMAC_CHAN0	/;"	d
STMMAC_COAL_TIMER	stmmac_main.c	/^#define STMMAC_COAL_TIMER(/;"	d	file:
STMMAC_COAL_TX_TIMER	common.h	/^#define STMMAC_COAL_TX_TIMER	/;"	d
STMMAC_DEFAULT_LIT_LS	common.h	/^#define STMMAC_DEFAULT_LIT_LS	/;"	d
STMMAC_DEFAULT_LPI_TIMER	stmmac_main.c	/^#define STMMAC_DEFAULT_LPI_TIMER	/;"	d	file:
STMMAC_DEFAULT_TWT_LS	common.h	/^#define STMMAC_DEFAULT_TWT_LS	/;"	d
STMMAC_DOWN	stmmac.h	/^	STMMAC_DOWN,$/;"	e	enum:stmmac_state
STMMAC_ETH	Kconfig	/^config STMMAC_ETH$/;"	c
STMMAC_FLOW_ACTION_DROP	stmmac.h	/^#define STMMAC_FLOW_ACTION_DROP	/;"	d
STMMAC_GET_ENTRY	common.h	/^#define STMMAC_GET_ENTRY(/;"	d
STMMAC_HWTS_ACTIVE	stmmac_main.c	/^#define STMMAC_HWTS_ACTIVE	/;"	d	file:
STMMAC_LB_TIMEOUT	stmmac_selftests.c	/^#define STMMAC_LB_TIMEOUT	/;"	d	file:
STMMAC_LOOPBACK_MAC	stmmac_selftests.c	/^#define STMMAC_LOOPBACK_MAC	/;"	d	file:
STMMAC_LOOPBACK_NONE	stmmac_selftests.c	/^#define STMMAC_LOOPBACK_NONE	/;"	d	file:
STMMAC_LOOPBACK_PHY	stmmac_selftests.c	/^#define STMMAC_LOOPBACK_PHY	/;"	d	file:
STMMAC_LPI_T	stmmac_main.c	/^#define STMMAC_LPI_T(/;"	d	file:
STMMAC_MAX_COAL_TX_TICK	common.h	/^#define STMMAC_MAX_COAL_TX_TICK	/;"	d
STMMAC_MMC_STAT	stmmac_ethtool.c	/^#define STMMAC_MMC_STAT(/;"	d	file:
STMMAC_MMC_STATS_LEN	stmmac_ethtool.c	/^#define STMMAC_MMC_STATS_LEN /;"	d	file:
STMMAC_PCI	Kconfig	/^config STMMAC_PCI$/;"	c
STMMAC_PCS_ASYM_PAUSE	common.h	/^#define STMMAC_PCS_ASYM_PAUSE	/;"	d
STMMAC_PCS_PAUSE	common.h	/^#define STMMAC_PCS_PAUSE	/;"	d
STMMAC_PCS_RGMII	common.h	/^#define STMMAC_PCS_RGMII	/;"	d
STMMAC_PCS_RTBI	common.h	/^#define STMMAC_PCS_RTBI	/;"	d
STMMAC_PCS_SGMII	common.h	/^#define STMMAC_PCS_SGMII	/;"	d
STMMAC_PCS_TBI	common.h	/^#define STMMAC_PCS_TBI	/;"	d
STMMAC_PLATFORM	Kconfig	/^config STMMAC_PLATFORM$/;"	c
STMMAC_PPS_MAX	stmmac.h	/^#define STMMAC_PPS_MAX	/;"	d
STMMAC_RESETING	stmmac.h	/^	STMMAC_RESETING,$/;"	e	enum:stmmac_state
STMMAC_RESET_REQUESTED	stmmac.h	/^	STMMAC_RESET_REQUESTED,$/;"	e	enum:stmmac_state
STMMAC_RESOURCE_NAME	stmmac.h	/^#define STMMAC_RESOURCE_NAME /;"	d
STMMAC_RING_MODE	common.h	/^#define STMMAC_RING_MODE	/;"	d
STMMAC_RSS_HASH_KEY_SIZE	common.h	/^#define STMMAC_RSS_HASH_KEY_SIZE	/;"	d
STMMAC_RSS_MAX_TABLE_SIZE	common.h	/^#define STMMAC_RSS_MAX_TABLE_SIZE	/;"	d
STMMAC_RX_COPYBREAK	stmmac_main.c	/^#define	STMMAC_RX_COPYBREAK	/;"	d	file:
STMMAC_RX_FRAMES	common.h	/^#define STMMAC_RX_FRAMES	/;"	d
STMMAC_RX_THRESH	stmmac_main.c	/^#define STMMAC_RX_THRESH(/;"	d	file:
STMMAC_SAFETY_FEAT_SIZE	common.h	/^#define STMMAC_SAFETY_FEAT_SIZE	/;"	d
STMMAC_SELFTESTS	Kconfig	/^config STMMAC_SELFTESTS$/;"	c
STMMAC_SERVICE_SCHED	stmmac.h	/^	STMMAC_SERVICE_SCHED,$/;"	e	enum:stmmac_state
STMMAC_STAT	stmmac_ethtool.c	/^#define STMMAC_STAT(/;"	d	file:
STMMAC_STATS_LEN	stmmac_ethtool.c	/^#define STMMAC_STATS_LEN /;"	d	file:
STMMAC_TBS_AVAIL	stmmac.h	/^#define STMMAC_TBS_AVAIL	/;"	d
STMMAC_TBS_EN	stmmac.h	/^#define STMMAC_TBS_EN	/;"	d
STMMAC_TBS_LT_OFFSET	stmmac_selftests.c	/^#define STMMAC_TBS_LT_OFFSET	/;"	d	file:
STMMAC_TEST_PKT_MAGIC	stmmac_selftests.c	/^#define STMMAC_TEST_PKT_MAGIC	/;"	d	file:
STMMAC_TEST_PKT_SIZE	stmmac_selftests.c	/^#define STMMAC_TEST_PKT_SIZE /;"	d	file:
STMMAC_TX_FRAMES	common.h	/^#define STMMAC_TX_FRAMES	/;"	d
STMMAC_TX_MAX_FRAMES	common.h	/^#define STMMAC_TX_MAX_FRAMES	/;"	d
STMMAC_TX_THRESH	stmmac_main.c	/^#define STMMAC_TX_THRESH(/;"	d	file:
STMMAC_VLAN_INSERT	common.h	/^#define STMMAC_VLAN_INSERT	/;"	d
STMMAC_VLAN_NONE	common.h	/^#define STMMAC_VLAN_NONE	/;"	d
STMMAC_VLAN_REMOVE	common.h	/^#define STMMAC_VLAN_REMOVE	/;"	d
STMMAC_VLAN_REPLACE	common.h	/^#define STMMAC_VLAN_REPLACE	/;"	d
STMMAC_VLAN_TAG_USED	common.h	/^#define STMMAC_VLAN_TAG_USED$/;"	d
SUN7I_GMAC_GMII_RGMII_RATE	dwmac-sunxi.c	/^#define SUN7I_GMAC_GMII_RGMII_RATE	/;"	d	file:
SUN7I_GMAC_MII_RATE	dwmac-sunxi.c	/^#define SUN7I_GMAC_MII_RATE	/;"	d	file:
SYSCFG_MCU_ETH_MASK	dwmac-stm32.c	/^#define SYSCFG_MCU_ETH_MASK	/;"	d	file:
SYSCFG_MCU_ETH_SEL_MII	dwmac-stm32.c	/^#define SYSCFG_MCU_ETH_SEL_MII	/;"	d	file:
SYSCFG_MCU_ETH_SEL_RMII	dwmac-stm32.c	/^#define SYSCFG_MCU_ETH_SEL_RMII	/;"	d	file:
SYSCFG_MP1_ETH_MASK	dwmac-stm32.c	/^#define SYSCFG_MP1_ETH_MASK	/;"	d	file:
SYSCFG_PMCCLRR_OFFSET	dwmac-stm32.c	/^#define SYSCFG_PMCCLRR_OFFSET	/;"	d	file:
SYSCFG_PMCR_ETH_CLK_SEL	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_CLK_SEL	/;"	d	file:
SYSCFG_PMCR_ETH_REF_CLK_SEL	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_REF_CLK_SEL	/;"	d	file:
SYSCFG_PMCR_ETH_SEL_GMII	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_SEL_GMII	/;"	d	file:
SYSCFG_PMCR_ETH_SEL_MII	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_SEL_MII	/;"	d	file:
SYSCFG_PMCR_ETH_SEL_RGMII	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_SEL_RGMII	/;"	d	file:
SYSCFG_PMCR_ETH_SEL_RMII	dwmac-stm32.c	/^#define SYSCFG_PMCR_ETH_SEL_RMII	/;"	d	file:
SYSCON_EPIT	dwmac-sun8i.c	/^#define SYSCON_EPIT	/;"	d	file:
SYSCON_ERXDC_SHIFT	dwmac-sun8i.c	/^#define SYSCON_ERXDC_SHIFT	/;"	d	file:
SYSCON_ETCS_EXT_GMII	dwmac-sun8i.c	/^#define SYSCON_ETCS_EXT_GMII	/;"	d	file:
SYSCON_ETCS_INT_GMII	dwmac-sun8i.c	/^#define SYSCON_ETCS_INT_GMII	/;"	d	file:
SYSCON_ETCS_MASK	dwmac-sun8i.c	/^#define SYSCON_ETCS_MASK	/;"	d	file:
SYSCON_ETCS_MII	dwmac-sun8i.c	/^#define SYSCON_ETCS_MII	/;"	d	file:
SYSCON_ETXDC_SHIFT	dwmac-sun8i.c	/^#define SYSCON_ETXDC_SHIFT	/;"	d	file:
SYSCON_RMII_EN	dwmac-sun8i.c	/^#define SYSCON_RMII_EN	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	altr_tse_pcs.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII /;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII	altr_tse_pcs.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII /;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII	altr_tse_pcs.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII /;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK	altr_tse_pcs.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK /;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH	altr_tse_pcs.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH	/;"	d	file:
SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH /;"	d	file:
SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK	dwmac-socfpga.c	/^#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK /;"	d	file:
SYSMGR_FPGAGRP_MODULE_EMAC	dwmac-socfpga.c	/^#define SYSMGR_FPGAGRP_MODULE_EMAC /;"	d	file:
SYSMGR_FPGAGRP_MODULE_REG	dwmac-socfpga.c	/^#define SYSMGR_FPGAGRP_MODULE_REG /;"	d	file:
SYSMGR_FPGAINTF_EMAC_BIT	dwmac-socfpga.c	/^#define SYSMGR_FPGAINTF_EMAC_BIT	/;"	d	file:
SYSMGR_FPGAINTF_EMAC_REG	dwmac-socfpga.c	/^#define SYSMGR_FPGAINTF_EMAC_REG	/;"	d	file:
SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK	dwmac-socfpga.c	/^#define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK /;"	d	file:
TCEIE	dwmac5.h	/^#define TCEIE	/;"	d
TC_DEFAULT	stmmac_main.c	/^#define TC_DEFAULT /;"	d	file:
TDES0_COLLISION_COUNT_MASK	descs.h	/^#define	TDES0_COLLISION_COUNT_MASK	/;"	d
TDES0_DEFERRED	descs.h	/^#define	TDES0_DEFERRED	/;"	d
TDES0_ERROR_SUMMARY	descs.h	/^#define	TDES0_ERROR_SUMMARY	/;"	d
TDES0_EXCESSIVE_COLLISIONS	descs.h	/^#define	TDES0_EXCESSIVE_COLLISIONS	/;"	d
TDES0_EXCESSIVE_DEFERRAL	descs.h	/^#define	TDES0_EXCESSIVE_DEFERRAL	/;"	d
TDES0_FRAME_FLUSHED	descs.h	/^#define	TDES0_FRAME_FLUSHED	/;"	d
TDES0_IP_HEADER_ERROR	descs.h	/^#define	TDES0_IP_HEADER_ERROR	/;"	d
TDES0_JABBER_TIMEOUT	descs.h	/^#define	TDES0_JABBER_TIMEOUT	/;"	d
TDES0_LATE_COLLISION	descs.h	/^#define	TDES0_LATE_COLLISION	/;"	d
TDES0_LOSS_CARRIER	descs.h	/^#define	TDES0_LOSS_CARRIER	/;"	d
TDES0_NO_CARRIER	descs.h	/^#define	TDES0_NO_CARRIER	/;"	d
TDES0_OWN	descs.h	/^#define	TDES0_OWN	/;"	d
TDES0_PAYLOAD_ERROR	descs.h	/^#define	TDES0_PAYLOAD_ERROR	/;"	d
TDES0_TIME_STAMP_STATUS	descs.h	/^#define	TDES0_TIME_STAMP_STATUS	/;"	d
TDES0_UNDERFLOW_ERROR	descs.h	/^#define	TDES0_UNDERFLOW_ERROR	/;"	d
TDES0_VLAN_FRAME	descs.h	/^#define	TDES0_VLAN_FRAME	/;"	d
TDES1_BUFFER1_SIZE_MASK	descs.h	/^#define	TDES1_BUFFER1_SIZE_MASK	/;"	d
TDES1_BUFFER2_SIZE_MASK	descs.h	/^#define	TDES1_BUFFER2_SIZE_MASK	/;"	d
TDES1_BUFFER2_SIZE_SHIFT	descs.h	/^#define	TDES1_BUFFER2_SIZE_SHIFT	/;"	d
TDES1_CHECKSUM_INSERTION_MASK	descs.h	/^#define	TDES1_CHECKSUM_INSERTION_MASK	/;"	d
TDES1_CHECKSUM_INSERTION_SHIFT	descs.h	/^#define	TDES1_CHECKSUM_INSERTION_SHIFT	/;"	d
TDES1_CRC_DISABLE	descs.h	/^#define	TDES1_CRC_DISABLE	/;"	d
TDES1_DISABLE_PADDING	descs.h	/^#define	TDES1_DISABLE_PADDING	/;"	d
TDES1_END_RING	descs.h	/^#define	TDES1_END_RING	/;"	d
TDES1_FIRST_SEGMENT	descs.h	/^#define	TDES1_FIRST_SEGMENT	/;"	d
TDES1_INTERRUPT	descs.h	/^#define	TDES1_INTERRUPT	/;"	d
TDES1_LAST_SEGMENT	descs.h	/^#define	TDES1_LAST_SEGMENT	/;"	d
TDES1_SECOND_ADDRESS_CHAINED	descs.h	/^#define	TDES1_SECOND_ADDRESS_CHAINED	/;"	d
TDES1_TIME_STAMP_ENABLE	descs.h	/^#define	TDES1_TIME_STAMP_ENABLE	/;"	d
TDES2_BUFFER1_SIZE_MASK	dwmac4_descs.h	/^#define TDES2_BUFFER1_SIZE_MASK	/;"	d
TDES2_BUFFER2_SIZE_MASK	dwmac4_descs.h	/^#define TDES2_BUFFER2_SIZE_MASK	/;"	d
TDES2_BUFFER2_SIZE_MASK_SHIFT	dwmac4_descs.h	/^#define TDES2_BUFFER2_SIZE_MASK_SHIFT	/;"	d
TDES2_INTERRUPT_ON_COMPLETION	dwmac4_descs.h	/^#define TDES2_INTERRUPT_ON_COMPLETION	/;"	d
TDES2_IVT_MASK	dwmac4_descs.h	/^#define TDES2_IVT_MASK	/;"	d
TDES2_IVT_SHIFT	dwmac4_descs.h	/^#define TDES2_IVT_SHIFT	/;"	d
TDES2_TIMESTAMP_ENABLE	dwmac4_descs.h	/^#define TDES2_TIMESTAMP_ENABLE	/;"	d
TDES2_VLAN_TAG_MASK	dwmac4_descs.h	/^#define TDES2_VLAN_TAG_MASK	/;"	d
TDES2_VLAN_TAG_SHIFT	dwmac4_descs.h	/^#define TDES2_VLAN_TAG_SHIFT	/;"	d
TDES3_CHECKSUM_INSERTION_MASK	dwmac4_descs.h	/^#define TDES3_CHECKSUM_INSERTION_MASK	/;"	d
TDES3_CHECKSUM_INSERTION_SHIFT	dwmac4_descs.h	/^#define TDES3_CHECKSUM_INSERTION_SHIFT	/;"	d
TDES3_COLLISION_COUNT_MASK	dwmac4_descs.h	/^#define TDES3_COLLISION_COUNT_MASK	/;"	d
TDES3_COLLISION_COUNT_SHIFT	dwmac4_descs.h	/^#define TDES3_COLLISION_COUNT_SHIFT	/;"	d
TDES3_CONTEXT_TYPE	dwmac4_descs.h	/^#define TDES3_CONTEXT_TYPE	/;"	d
TDES3_CONTEXT_TYPE_SHIFT	dwmac4_descs.h	/^#define	TDES3_CONTEXT_TYPE_SHIFT	/;"	d
TDES3_CRC_PAD_CTRL_MASK	dwmac4_descs.h	/^#define TDES3_CRC_PAD_CTRL_MASK	/;"	d
TDES3_CTXT_TCMSSV	dwmac4_descs.h	/^#define TDES3_CTXT_TCMSSV	/;"	d
TDES3_DEFERRED	dwmac4_descs.h	/^#define TDES3_DEFERRED	/;"	d
TDES3_ERROR_SUMMARY	dwmac4_descs.h	/^#define TDES3_ERROR_SUMMARY	/;"	d
TDES3_EXCESSIVE_COLLISION	dwmac4_descs.h	/^#define TDES3_EXCESSIVE_COLLISION	/;"	d
TDES3_EXCESSIVE_DEFERRAL	dwmac4_descs.h	/^#define TDES3_EXCESSIVE_DEFERRAL	/;"	d
TDES3_FIRST_DESCRIPTOR	dwmac4_descs.h	/^#define TDES3_FIRST_DESCRIPTOR	/;"	d
TDES3_HDR_LEN_SHIFT	dwmac4_descs.h	/^#define TDES3_HDR_LEN_SHIFT	/;"	d
TDES3_IP_HDR_ERROR	dwmac4_descs.h	/^#define TDES3_IP_HDR_ERROR	/;"	d
TDES3_IVLTV	dwmac4_descs.h	/^#define TDES3_IVLTV	/;"	d
TDES3_IVTIR_MASK	dwmac4_descs.h	/^#define TDES3_IVTIR_MASK	/;"	d
TDES3_IVTIR_SHIFT	dwmac4_descs.h	/^#define TDES3_IVTIR_SHIFT	/;"	d
TDES3_JABBER_TIMEOUT	dwmac4_descs.h	/^#define TDES3_JABBER_TIMEOUT	/;"	d
TDES3_LAST_DESCRIPTOR	dwmac4_descs.h	/^#define TDES3_LAST_DESCRIPTOR	/;"	d
TDES3_LAST_DESCRIPTOR_SHIFT	dwmac4_descs.h	/^#define TDES3_LAST_DESCRIPTOR_SHIFT	/;"	d
TDES3_LATE_COLLISION	dwmac4_descs.h	/^#define TDES3_LATE_COLLISION	/;"	d
TDES3_LOSS_CARRIER	dwmac4_descs.h	/^#define TDES3_LOSS_CARRIER	/;"	d
TDES3_NO_CARRIER	dwmac4_descs.h	/^#define TDES3_NO_CARRIER	/;"	d
TDES3_OWN	dwmac4_descs.h	/^#define TDES3_OWN	/;"	d
TDES3_OWN_SHIFT	dwmac4_descs.h	/^#define TDES3_OWN_SHIFT	/;"	d
TDES3_PACKET_FLUSHED	dwmac4_descs.h	/^#define TDES3_PACKET_FLUSHED	/;"	d
TDES3_PACKET_SIZE_MASK	dwmac4_descs.h	/^#define TDES3_PACKET_SIZE_MASK	/;"	d
TDES3_PAYLOAD_ERROR	dwmac4_descs.h	/^#define TDES3_PAYLOAD_ERROR	/;"	d
TDES3_RS1V	dwmac4_descs.h	/^#define	TDES3_RS1V	/;"	d
TDES3_RS1V_SHIFT	dwmac4_descs.h	/^#define	TDES3_RS1V_SHIFT	/;"	d
TDES3_SA_INSERT_CTRL_MASK	dwmac4_descs.h	/^#define TDES3_SA_INSERT_CTRL_MASK	/;"	d
TDES3_SA_INSERT_CTRL_SHIFT	dwmac4_descs.h	/^#define TDES3_SA_INSERT_CTRL_SHIFT	/;"	d
TDES3_SLOT_NUMBER_MASK	dwmac4_descs.h	/^#define TDES3_SLOT_NUMBER_MASK	/;"	d
TDES3_TCP_PKT_PAYLOAD_MASK	dwmac4_descs.h	/^#define TDES3_TCP_PKT_PAYLOAD_MASK	/;"	d
TDES3_TCP_SEGMENTATION_ENABLE	dwmac4_descs.h	/^#define TDES3_TCP_SEGMENTATION_ENABLE	/;"	d
TDES3_TIMESTAMP_STATUS	dwmac4_descs.h	/^#define TDES3_TIMESTAMP_STATUS	/;"	d
TDES3_TIMESTAMP_STATUS_SHIFT	dwmac4_descs.h	/^#define TDES3_TIMESTAMP_STATUS_SHIFT	/;"	d
TDES3_UNDERFLOW_ERROR	dwmac4_descs.h	/^#define TDES3_UNDERFLOW_ERROR	/;"	d
TDES3_VLAN_TAG	dwmac4_descs.h	/^#define TDES3_VLAN_TAG	/;"	d
TDES3_VLTV	dwmac4_descs.h	/^#define TDES3_VLTV	/;"	d
TDES4_LT	dwmac4_descs.h	/^#define TDES4_LT	/;"	d
TDES4_LTV	dwmac4_descs.h	/^#define TDES4_LTV	/;"	d
TDES5_LT	dwmac4_descs.h	/^#define TDES5_LT	/;"	d
TER	dwmac5.h	/^#define TER	/;"	d
TMOUTEN	dwmac5.h	/^#define TMOUTEN	/;"	d
TRGTBUSY0	dwmac5.h	/^#define TRGTBUSY0	/;"	d
TRGTMODSELx	dwmac5.h	/^#define TRGTMODSELx(/;"	d
TSE_PCS_CONTROL_AN_EN_MASK	altr_tse_pcs.c	/^#define TSE_PCS_CONTROL_AN_EN_MASK	/;"	d	file:
TSE_PCS_CONTROL_REG	altr_tse_pcs.c	/^#define TSE_PCS_CONTROL_REG	/;"	d	file:
TSE_PCS_CONTROL_RESTART_AN_MASK	altr_tse_pcs.c	/^#define TSE_PCS_CONTROL_RESTART_AN_MASK	/;"	d	file:
TSE_PCS_CTRL_AUTONEG_SGMII	altr_tse_pcs.c	/^#define TSE_PCS_CTRL_AUTONEG_SGMII	/;"	d	file:
TSE_PCS_IF_MODE_REG	altr_tse_pcs.c	/^#define TSE_PCS_IF_MODE_REG	/;"	d	file:
TSE_PCS_IF_USE_SGMII	altr_tse_pcs.c	/^#define TSE_PCS_IF_USE_SGMII	/;"	d	file:
TSE_PCS_LINK_TIMER_0_REG	altr_tse_pcs.c	/^#define TSE_PCS_LINK_TIMER_0_REG	/;"	d	file:
TSE_PCS_LINK_TIMER_1_REG	altr_tse_pcs.c	/^#define TSE_PCS_LINK_TIMER_1_REG	/;"	d	file:
TSE_PCS_PARTNER_ABILITY_REG	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_ABILITY_REG	/;"	d	file:
TSE_PCS_PARTNER_DUPLEX_FULL	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_DUPLEX_FULL	/;"	d	file:
TSE_PCS_PARTNER_DUPLEX_HALF	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_DUPLEX_HALF	/;"	d	file:
TSE_PCS_PARTNER_DUPLEX_MASK	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_DUPLEX_MASK	/;"	d	file:
TSE_PCS_PARTNER_SPEED_10	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_SPEED_10	/;"	d	file:
TSE_PCS_PARTNER_SPEED_100	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_SPEED_100	/;"	d	file:
TSE_PCS_PARTNER_SPEED_1000	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_SPEED_1000	/;"	d	file:
TSE_PCS_PARTNER_SPEED_MASK	altr_tse_pcs.c	/^#define TSE_PCS_PARTNER_SPEED_MASK	/;"	d	file:
TSE_PCS_SGMII_LINK_TIMER_0	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_LINK_TIMER_0	/;"	d	file:
TSE_PCS_SGMII_LINK_TIMER_1	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_LINK_TIMER_1	/;"	d	file:
TSE_PCS_SGMII_SPEED_10	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_SPEED_10	/;"	d	file:
TSE_PCS_SGMII_SPEED_100	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_SPEED_100	/;"	d	file:
TSE_PCS_SGMII_SPEED_1000	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_SPEED_1000	/;"	d	file:
TSE_PCS_SGMII_SPEED_MASK	altr_tse_pcs.c	/^#define TSE_PCS_SGMII_SPEED_MASK	/;"	d	file:
TSE_PCS_SIZE	altr_tse_pcs.c	/^#define TSE_PCS_SIZE	/;"	d	file:
TSE_PCS_STATUS_AN_COMPLETED_MASK	altr_tse_pcs.c	/^#define TSE_PCS_STATUS_AN_COMPLETED_MASK	/;"	d	file:
TSE_PCS_STATUS_LINK_MASK	altr_tse_pcs.c	/^#define TSE_PCS_STATUS_LINK_MASK	/;"	d	file:
TSE_PCS_STATUS_REG	altr_tse_pcs.c	/^#define TSE_PCS_STATUS_REG	/;"	d	file:
TSE_PCS_SW_RESET_TIMEOUT	altr_tse_pcs.c	/^#define TSE_PCS_SW_RESET_TIMEOUT	/;"	d	file:
TSE_PCS_SW_RST_MASK	altr_tse_pcs.c	/^#define TSE_PCS_SW_RST_MASK	/;"	d	file:
TSE_PCS_USE_SGMII_AN_MASK	altr_tse_pcs.c	/^#define TSE_PCS_USE_SGMII_AN_MASK	/;"	d	file:
TSE_PCS_USE_SGMII_ENA	altr_tse_pcs.c	/^#define TSE_PCS_USE_SGMII_ENA	/;"	d	file:
TSOEE	dwmac5.h	/^#define TSOEE	/;"	d
TSO_MAX_BUFF_SIZE	stmmac_main.c	/^#define	TSO_MAX_BUFF_SIZE	/;"	d	file:
TTSL0	dwmac5.h	/^#define TTSL0	/;"	d
TXCEIE	dwmac5.h	/^#define TXCEIE	/;"	d
TX_CIC_FULL	descs.h	/^#define	TX_CIC_FULL	/;"	d
TX_RETIME_SRC_CLKGEN	dwmac-sti.c	/^	TX_RETIME_SRC_CLKGEN,$/;"	e	enum:__anon3897d81f0103	file:
TX_RETIME_SRC_CLK_125	dwmac-sti.c	/^	TX_RETIME_SRC_CLK_125,$/;"	e	enum:__anon3897d81f0103	file:
TX_RETIME_SRC_NA	dwmac-sti.c	/^	TX_RETIME_SRC_NA = 0,$/;"	e	enum:__anon3897d81f0103	file:
TX_RETIME_SRC_PHYCLK	dwmac-sti.c	/^	TX_RETIME_SRC_PHYCLK,$/;"	e	enum:__anon3897d81f0103	file:
TX_RETIME_SRC_TXCLK	dwmac-sti.c	/^	TX_RETIME_SRC_TXCLK = 1,$/;"	e	enum:__anon3897d81f0103	file:
TX_TIMEO	stmmac_main.c	/^#define TX_TIMEO	/;"	d	file:
WRRDN	dwmac5.h	/^#define WRRDN	/;"	d
XGMAC_AAL	dwxgmac2.h	/^#define XGMAC_AAL	/;"	d
XGMAC_ABPSIS	dwxgmac2.h	/^#define XGMAC_ABPSIS	/;"	d
XGMAC_ADDR	dwxgmac2.h	/^#define XGMAC_ADDR	/;"	d
XGMAC_ADDRT	dwxgmac2.h	/^#define XGMAC_ADDRT	/;"	d
XGMAC_ADDR_MAX	dwxgmac2.h	/^#define XGMAC_ADDR_MAX	/;"	d
XGMAC_ADDR_SHIFT	dwxgmac2.h	/^#define XGMAC_ADDR_SHIFT	/;"	d
XGMAC_ADDRx_HIGH	dwxgmac2.h	/^#define XGMAC_ADDRx_HIGH(/;"	d
XGMAC_ADDRx_LOW	dwxgmac2.h	/^#define XGMAC_ADDRx_LOW(/;"	d
XGMAC_AE	dwxgmac2.h	/^#define XGMAC_AE	/;"	d
XGMAC_AIE	dwxgmac2.h	/^#define XGMAC_AIE	/;"	d
XGMAC_AIS	dwxgmac2.h	/^#define XGMAC_AIS	/;"	d
XGMAC_ARP_ADDR	dwxgmac2.h	/^#define XGMAC_ARP_ADDR	/;"	d
XGMAC_BLEN	dwxgmac2.h	/^#define XGMAC_BLEN	/;"	d
XGMAC_BLEN128	dwxgmac2.h	/^#define XGMAC_BLEN128	/;"	d
XGMAC_BLEN16	dwxgmac2.h	/^#define XGMAC_BLEN16	/;"	d
XGMAC_BLEN256	dwxgmac2.h	/^#define XGMAC_BLEN256	/;"	d
XGMAC_BLEN32	dwxgmac2.h	/^#define XGMAC_BLEN32	/;"	d
XGMAC_BLEN4	dwxgmac2.h	/^#define XGMAC_BLEN4	/;"	d
XGMAC_BLEN64	dwxgmac2.h	/^#define XGMAC_BLEN64	/;"	d
XGMAC_BLEN8	dwxgmac2.h	/^#define XGMAC_BLEN8	/;"	d
XGMAC_BTR_HIGH	dwxgmac2.h	/^#define XGMAC_BTR_HIGH	/;"	d
XGMAC_BTR_LOW	dwxgmac2.h	/^#define XGMAC_BTR_LOW	/;"	d
XGMAC_CBS	dwxgmac2.h	/^#define XGMAC_CBS	/;"	d
XGMAC_CC	dwxgmac2.h	/^#define XGMAC_CC	/;"	d
XGMAC_CONFIG_ACS	dwxgmac2.h	/^#define XGMAC_CONFIG_ACS	/;"	d
XGMAC_CONFIG_ARPEN	dwxgmac2.h	/^#define XGMAC_CONFIG_ARPEN	/;"	d
XGMAC_CONFIG_CST	dwxgmac2.h	/^#define XGMAC_CONFIG_CST	/;"	d
XGMAC_CONFIG_GPSL	dwxgmac2.h	/^#define XGMAC_CONFIG_GPSL	/;"	d
XGMAC_CONFIG_GPSLCE	dwxgmac2.h	/^#define XGMAC_CONFIG_GPSLCE	/;"	d
XGMAC_CONFIG_GPSL_SHIFT	dwxgmac2.h	/^#define XGMAC_CONFIG_GPSL_SHIFT	/;"	d
XGMAC_CONFIG_HDSMS	dwxgmac2.h	/^#define XGMAC_CONFIG_HDSMS	/;"	d
XGMAC_CONFIG_HDSMS_256	dwxgmac2.h	/^#define XGMAC_CONFIG_HDSMS_256	/;"	d
XGMAC_CONFIG_HDSMS_SHIFT	dwxgmac2.h	/^#define XGMAC_CONFIG_HDSMS_SHIFT	/;"	d
XGMAC_CONFIG_IPC	dwxgmac2.h	/^#define XGMAC_CONFIG_IPC	/;"	d
XGMAC_CONFIG_JD	dwxgmac2.h	/^#define XGMAC_CONFIG_JD	/;"	d
XGMAC_CONFIG_JE	dwxgmac2.h	/^#define XGMAC_CONFIG_JE	/;"	d
XGMAC_CONFIG_LM	dwxgmac2.h	/^#define XGMAC_CONFIG_LM	/;"	d
XGMAC_CONFIG_RE	dwxgmac2.h	/^#define XGMAC_CONFIG_RE	/;"	d
XGMAC_CONFIG_S2KP	dwxgmac2.h	/^#define XGMAC_CONFIG_S2KP	/;"	d
XGMAC_CONFIG_SARC	dwxgmac2.h	/^#define XGMAC_CONFIG_SARC	/;"	d
XGMAC_CONFIG_SARC_SHIFT	dwxgmac2.h	/^#define XGMAC_CONFIG_SARC_SHIFT	/;"	d
XGMAC_CONFIG_SS_10000	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_10000	/;"	d
XGMAC_CONFIG_SS_1000_GMII	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_1000_GMII	/;"	d
XGMAC_CONFIG_SS_100_MII	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_100_MII	/;"	d
XGMAC_CONFIG_SS_10_MII	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_10_MII	/;"	d
XGMAC_CONFIG_SS_2500	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_2500	/;"	d
XGMAC_CONFIG_SS_2500_GMII	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_2500_GMII	/;"	d
XGMAC_CONFIG_SS_5000	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_5000	/;"	d
XGMAC_CONFIG_SS_MASK	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_MASK	/;"	d
XGMAC_CONFIG_SS_OFF	dwxgmac2.h	/^#define XGMAC_CONFIG_SS_OFF	/;"	d
XGMAC_CONFIG_TE	dwxgmac2.h	/^#define XGMAC_CONFIG_TE	/;"	d
XGMAC_CONFIG_WD	dwxgmac2.h	/^#define XGMAC_CONFIG_WD	/;"	d
XGMAC_CORE_INIT_RX	dwxgmac2.h	/^#define XGMAC_CORE_INIT_RX	/;"	d
XGMAC_CORE_INIT_TX	dwxgmac2.h	/^#define XGMAC_CORE_INIT_TX	/;"	d
XGMAC_CT	dwxgmac2.h	/^#define XGMAC_CT	/;"	d
XGMAC_CTR_HIGH	dwxgmac2.h	/^#define XGMAC_CTR_HIGH	/;"	d
XGMAC_CTR_LOW	dwxgmac2.h	/^#define XGMAC_CTR_LOW	/;"	d
XGMAC_DCEIE	dwxgmac2.h	/^#define XGMAC_DCEIE	/;"	d
XGMAC_DCS	dwxgmac2.h	/^#define XGMAC_DCS	/;"	d
XGMAC_DCS_SHIFT	dwxgmac2.h	/^#define XGMAC_DCS_SHIFT	/;"	d
XGMAC_DECIS	dwxgmac2.h	/^#define XGMAC_DECIS	/;"	d
XGMAC_DEF_FTOS	dwxgmac2.h	/^#define XGMAC_DEF_FTOS	/;"	d
XGMAC_DEUIS	dwxgmac2.h	/^#define XGMAC_DEUIS	/;"	d
XGMAC_DMA_CH_CONTROL	dwxgmac2.h	/^#define XGMAC_DMA_CH_CONTROL(/;"	d
XGMAC_DMA_CH_INT_EN	dwxgmac2.h	/^#define XGMAC_DMA_CH_INT_EN(/;"	d
XGMAC_DMA_CH_RX_CONTROL	dwxgmac2.h	/^#define XGMAC_DMA_CH_RX_CONTROL(/;"	d
XGMAC_DMA_CH_RxDESC_HADDR	dwxgmac2.h	/^#define XGMAC_DMA_CH_RxDESC_HADDR(/;"	d
XGMAC_DMA_CH_RxDESC_LADDR	dwxgmac2.h	/^#define XGMAC_DMA_CH_RxDESC_LADDR(/;"	d
XGMAC_DMA_CH_RxDESC_RING_LEN	dwxgmac2.h	/^#define XGMAC_DMA_CH_RxDESC_RING_LEN(/;"	d
XGMAC_DMA_CH_RxDESC_TAIL_LPTR	dwxgmac2.h	/^#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(/;"	d
XGMAC_DMA_CH_Rx_WATCHDOG	dwxgmac2.h	/^#define XGMAC_DMA_CH_Rx_WATCHDOG(/;"	d
XGMAC_DMA_CH_STATUS	dwxgmac2.h	/^#define XGMAC_DMA_CH_STATUS(/;"	d
XGMAC_DMA_CH_TX_CONTROL	dwxgmac2.h	/^#define XGMAC_DMA_CH_TX_CONTROL(/;"	d
XGMAC_DMA_CH_TxDESC_HADDR	dwxgmac2.h	/^#define XGMAC_DMA_CH_TxDESC_HADDR(/;"	d
XGMAC_DMA_CH_TxDESC_LADDR	dwxgmac2.h	/^#define XGMAC_DMA_CH_TxDESC_LADDR(/;"	d
XGMAC_DMA_CH_TxDESC_RING_LEN	dwxgmac2.h	/^#define XGMAC_DMA_CH_TxDESC_RING_LEN(/;"	d
XGMAC_DMA_CH_TxDESC_TAIL_LPTR	dwxgmac2.h	/^#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(/;"	d
XGMAC_DMA_ECC_INT_ENABLE	dwxgmac2.h	/^#define XGMAC_DMA_ECC_INT_ENABLE	/;"	d
XGMAC_DMA_ECC_INT_STATUS	dwxgmac2.h	/^#define XGMAC_DMA_ECC_INT_STATUS	/;"	d
XGMAC_DMA_INT_DEFAULT_EN	dwxgmac2.h	/^#define XGMAC_DMA_INT_DEFAULT_EN	/;"	d
XGMAC_DMA_INT_DEFAULT_RX	dwxgmac2.h	/^#define XGMAC_DMA_INT_DEFAULT_RX	/;"	d
XGMAC_DMA_INT_DEFAULT_TX	dwxgmac2.h	/^#define XGMAC_DMA_INT_DEFAULT_TX	/;"	d
XGMAC_DMA_MODE	dwxgmac2.h	/^#define XGMAC_DMA_MODE	/;"	d
XGMAC_DMA_SAFETY_INT_STATUS	dwxgmac2.h	/^#define XGMAC_DMA_SAFETY_INT_STATUS	/;"	d
XGMAC_DMA_SYSBUS_MODE	dwxgmac2.h	/^#define XGMAC_DMA_SYSBUS_MODE	/;"	d
XGMAC_DMA_TBS_CTRL0	dwxgmac2.h	/^#define XGMAC_DMA_TBS_CTRL0	/;"	d
XGMAC_DMA_TBS_CTRL1	dwxgmac2.h	/^#define XGMAC_DMA_TBS_CTRL1	/;"	d
XGMAC_DMA_TBS_CTRL2	dwxgmac2.h	/^#define XGMAC_DMA_TBS_CTRL2	/;"	d
XGMAC_DMA_TBS_CTRL3	dwxgmac2.h	/^#define XGMAC_DMA_TBS_CTRL3	/;"	d
XGMAC_DWRR	dwxgmac2.h	/^#define XGMAC_DWRR	/;"	d
XGMAC_EAME	dwxgmac2.h	/^#define XGMAC_EAME	/;"	d
XGMAC_ECEIE	dwxgmac2.h	/^#define XGMAC_ECEIE	/;"	d
XGMAC_EDSE	dwxgmac2.h	/^#define XGMAC_EDSE	/;"	d
XGMAC_EEST	dwxgmac2.h	/^#define XGMAC_EEST	/;"	d
XGMAC_EFPE	dwxgmac2.h	/^#define XGMAC_EFPE	/;"	d
XGMAC_EHFC	dwxgmac2.h	/^#define XGMAC_EHFC	/;"	d
XGMAC_EN_LPI	dwxgmac2.h	/^#define XGMAC_EN_LPI	/;"	d
XGMAC_ETHTOOL_NAME	stmmac_ethtool.c	/^#define XGMAC_ETHTOOL_NAME	/;"	d	file:
XGMAC_ETS	dwxgmac2.h	/^#define XGMAC_ETS	/;"	d
XGMAC_ETSALG	dwxgmac2.h	/^#define XGMAC_ETSALG	/;"	d
XGMAC_FBE	dwxgmac2.h	/^#define XGMAC_FBE	/;"	d
XGMAC_FILTER_HMC	dwxgmac2.h	/^#define XGMAC_FILTER_HMC	/;"	d
XGMAC_FILTER_HPF	dwxgmac2.h	/^#define XGMAC_FILTER_HPF	/;"	d
XGMAC_FILTER_IPFE	dwxgmac2.h	/^#define XGMAC_FILTER_IPFE	/;"	d
XGMAC_FILTER_PCF	dwxgmac2.h	/^#define XGMAC_FILTER_PCF	/;"	d
XGMAC_FILTER_PM	dwxgmac2.h	/^#define XGMAC_FILTER_PM	/;"	d
XGMAC_FILTER_PR	dwxgmac2.h	/^#define XGMAC_FILTER_PR	/;"	d
XGMAC_FILTER_RA	dwxgmac2.h	/^#define XGMAC_FILTER_RA	/;"	d
XGMAC_FILTER_VTFE	dwxgmac2.h	/^#define XGMAC_FILTER_VTFE	/;"	d
XGMAC_FPE_CTRL_STS	dwxgmac2.h	/^#define XGMAC_FPE_CTRL_STS	/;"	d
XGMAC_FRPE	dwxgmac2.h	/^#define XGMAC_FRPE	/;"	d
XGMAC_FTOS	dwxgmac2.h	/^#define XGMAC_FTOS	/;"	d
XGMAC_FTOV	dwxgmac2.h	/^#define XGMAC_FTOV	/;"	d
XGMAC_GCRR	dwxgmac2.h	/^#define XGMAC_GCRR	/;"	d
XGMAC_GLBLUCAST	dwxgmac2.h	/^#define XGMAC_GLBLUCAST	/;"	d
XGMAC_HASH_TABLE	dwxgmac2.h	/^#define XGMAC_HASH_TABLE(/;"	d
XGMAC_HWFEAT_ADDR64	dwxgmac2.h	/^#define XGMAC_HWFEAT_ADDR64	/;"	d
XGMAC_HWFEAT_ARPOFFSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_ARPOFFSEL	/;"	d
XGMAC_HWFEAT_ASP	dwxgmac2.h	/^#define XGMAC_HWFEAT_ASP	/;"	d
XGMAC_HWFEAT_AVSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_AVSEL	/;"	d
XGMAC_HWFEAT_DVLAN	dwxgmac2.h	/^#define XGMAC_HWFEAT_DVLAN	/;"	d
XGMAC_HWFEAT_EEESEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_EEESEL	/;"	d
XGMAC_HWFEAT_ESTDEP	dwxgmac2.h	/^#define XGMAC_HWFEAT_ESTDEP	/;"	d
XGMAC_HWFEAT_ESTSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_ESTSEL	/;"	d
XGMAC_HWFEAT_ESTWID	dwxgmac2.h	/^#define XGMAC_HWFEAT_ESTWID	/;"	d
XGMAC_HWFEAT_FPESEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_FPESEL	/;"	d
XGMAC_HWFEAT_FRPES	dwxgmac2.h	/^#define XGMAC_HWFEAT_FRPES	/;"	d
XGMAC_HWFEAT_FRPPB	dwxgmac2.h	/^#define XGMAC_HWFEAT_FRPPB	/;"	d
XGMAC_HWFEAT_FRPSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_FRPSEL	/;"	d
XGMAC_HWFEAT_GMIISEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_GMIISEL	/;"	d
XGMAC_HWFEAT_HASHTBLSZ	dwxgmac2.h	/^#define XGMAC_HWFEAT_HASHTBLSZ	/;"	d
XGMAC_HWFEAT_L3L4FNUM	dwxgmac2.h	/^#define XGMAC_HWFEAT_L3L4FNUM	/;"	d
XGMAC_HWFEAT_MGKSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_MGKSEL	/;"	d
XGMAC_HWFEAT_MMCSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_MMCSEL	/;"	d
XGMAC_HWFEAT_PPSOUTNUM	dwxgmac2.h	/^#define XGMAC_HWFEAT_PPSOUTNUM	/;"	d
XGMAC_HWFEAT_RAVSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_RAVSEL	/;"	d
XGMAC_HWFEAT_RSSEN	dwxgmac2.h	/^#define XGMAC_HWFEAT_RSSEN	/;"	d
XGMAC_HWFEAT_RWKSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_RWKSEL	/;"	d
XGMAC_HWFEAT_RXCHCNT	dwxgmac2.h	/^#define XGMAC_HWFEAT_RXCHCNT	/;"	d
XGMAC_HWFEAT_RXCOESEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_RXCOESEL	/;"	d
XGMAC_HWFEAT_RXFIFOSIZE	dwxgmac2.h	/^#define XGMAC_HWFEAT_RXFIFOSIZE	/;"	d
XGMAC_HWFEAT_RXQCNT	dwxgmac2.h	/^#define XGMAC_HWFEAT_RXQCNT	/;"	d
XGMAC_HWFEAT_SAVLANINS	dwxgmac2.h	/^#define XGMAC_HWFEAT_SAVLANINS	/;"	d
XGMAC_HWFEAT_SPHEN	dwxgmac2.h	/^#define XGMAC_HWFEAT_SPHEN	/;"	d
XGMAC_HWFEAT_TBSSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_TBSSEL	/;"	d
XGMAC_HWFEAT_TSOEN	dwxgmac2.h	/^#define XGMAC_HWFEAT_TSOEN	/;"	d
XGMAC_HWFEAT_TSSEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_TSSEL	/;"	d
XGMAC_HWFEAT_TXCHCNT	dwxgmac2.h	/^#define XGMAC_HWFEAT_TXCHCNT	/;"	d
XGMAC_HWFEAT_TXCOESEL	dwxgmac2.h	/^#define XGMAC_HWFEAT_TXCOESEL	/;"	d
XGMAC_HWFEAT_TXFIFOSIZE	dwxgmac2.h	/^#define XGMAC_HWFEAT_TXFIFOSIZE	/;"	d
XGMAC_HWFEAT_TXQCNT	dwxgmac2.h	/^#define XGMAC_HWFEAT_TXQCNT	/;"	d
XGMAC_HWFEAT_VLHASH	dwxgmac2.h	/^#define XGMAC_HWFEAT_VLHASH	/;"	d
XGMAC_HW_FEATURE0	dwxgmac2.h	/^#define XGMAC_HW_FEATURE0	/;"	d
XGMAC_HW_FEATURE1	dwxgmac2.h	/^#define XGMAC_HW_FEATURE1	/;"	d
XGMAC_HW_FEATURE2	dwxgmac2.h	/^#define XGMAC_HW_FEATURE2	/;"	d
XGMAC_HW_FEATURE3	dwxgmac2.h	/^#define XGMAC_HW_FEATURE3	/;"	d
XGMAC_IDDR	dwxgmac2.h	/^#define XGMAC_IDDR	/;"	d
XGMAC_IDDR_FNUM	dwxgmac2.h	/^#define XGMAC_IDDR_FNUM	/;"	d
XGMAC_IDDR_SHIFT	dwxgmac2.h	/^#define XGMAC_IDDR_SHIFT	/;"	d
XGMAC_INT_DEFAULT_EN	dwxgmac2.h	/^#define XGMAC_INT_DEFAULT_EN	/;"	d
XGMAC_INT_EN	dwxgmac2.h	/^#define XGMAC_INT_EN	/;"	d
XGMAC_INT_STATUS	dwxgmac2.h	/^#define XGMAC_INT_STATUS	/;"	d
XGMAC_IP2TE	dwxgmac2.h	/^#define XGMAC_IP2TE	/;"	d
XGMAC_JUMBO_LEN	dwxgmac2.h	/^#define XGMAC_JUMBO_LEN	/;"	d
XGMAC_L34T_IP4TCP	dwxgmac2.h	/^#define XGMAC_L34T_IP4TCP	/;"	d
XGMAC_L34T_IP4UDP	dwxgmac2.h	/^#define XGMAC_L34T_IP4UDP	/;"	d
XGMAC_L34T_IP6TCP	dwxgmac2.h	/^#define XGMAC_L34T_IP6TCP	/;"	d
XGMAC_L34T_IP6UDP	dwxgmac2.h	/^#define XGMAC_L34T_IP6UDP	/;"	d
XGMAC_L3DAIM0	dwxgmac2.h	/^#define XGMAC_L3DAIM0	/;"	d
XGMAC_L3DAM0	dwxgmac2.h	/^#define XGMAC_L3DAM0	/;"	d
XGMAC_L3HDBM0	dwxgmac2.h	/^#define XGMAC_L3HDBM0	/;"	d
XGMAC_L3HSBM0	dwxgmac2.h	/^#define XGMAC_L3HSBM0	/;"	d
XGMAC_L3L4_ADDR_CTRL	dwxgmac2.h	/^#define XGMAC_L3L4_ADDR_CTRL	/;"	d
XGMAC_L3L4_CTRL	dwxgmac2.h	/^#define XGMAC_L3L4_CTRL	/;"	d
XGMAC_L3L4_DATA	dwxgmac2.h	/^#define XGMAC_L3L4_DATA	/;"	d
XGMAC_L3PEN0	dwxgmac2.h	/^#define XGMAC_L3PEN0	/;"	d
XGMAC_L3SAIM0	dwxgmac2.h	/^#define XGMAC_L3SAIM0	/;"	d
XGMAC_L3SAM0	dwxgmac2.h	/^#define XGMAC_L3SAM0	/;"	d
XGMAC_L3_ADDR0	dwxgmac2.h	/^#define XGMAC_L3_ADDR0	/;"	d
XGMAC_L3_ADDR1	dwxgmac2.h	/^#define XGMAC_L3_ADDR1	/;"	d
XGMAC_L3_ADDR2	dwxgmac2.h	/^#define XGMAC_L3_ADDR2	/;"	d
XGMAC_L4DP0	dwxgmac2.h	/^#define XGMAC_L4DP0	/;"	d
XGMAC_L4DP0_SHIFT	dwxgmac2.h	/^#define XGMAC_L4DP0_SHIFT	/;"	d
XGMAC_L4DPIM0	dwxgmac2.h	/^#define XGMAC_L4DPIM0	/;"	d
XGMAC_L4DPM0	dwxgmac2.h	/^#define XGMAC_L4DPM0	/;"	d
XGMAC_L4PEN0	dwxgmac2.h	/^#define XGMAC_L4PEN0	/;"	d
XGMAC_L4SP0	dwxgmac2.h	/^#define XGMAC_L4SP0	/;"	d
XGMAC_L4SPIM0	dwxgmac2.h	/^#define XGMAC_L4SPIM0	/;"	d
XGMAC_L4SPM0	dwxgmac2.h	/^#define XGMAC_L4SPM0	/;"	d
XGMAC_L4_ADDR	dwxgmac2.h	/^#define XGMAC_L4_ADDR	/;"	d
XGMAC_LLR	dwxgmac2.h	/^#define XGMAC_LLR	/;"	d
XGMAC_LPIIE	dwxgmac2.h	/^#define XGMAC_LPIIE	/;"	d
XGMAC_LPIIS	dwxgmac2.h	/^#define XGMAC_LPIIS	/;"	d
XGMAC_LPITXA	dwxgmac2.h	/^#define XGMAC_LPITXA	/;"	d
XGMAC_LPITXEN	dwxgmac2.h	/^#define XGMAC_LPITXEN	/;"	d
XGMAC_LPI_CTRL	dwxgmac2.h	/^#define XGMAC_LPI_CTRL	/;"	d
XGMAC_LPI_TIMER_CTRL	dwxgmac2.h	/^#define XGMAC_LPI_TIMER_CTRL	/;"	d
XGMAC_LPI_XIT_PKT	dwxgmac2.h	/^#define XGMAC_LPI_XIT_PKT	/;"	d
XGMAC_MAC_DPP_FSM_INT_STATUS	dwxgmac2.h	/^#define XGMAC_MAC_DPP_FSM_INT_STATUS	/;"	d
XGMAC_MAC_FSM_CONTROL	dwxgmac2.h	/^#define XGMAC_MAC_FSM_CONTROL	/;"	d
XGMAC_MAC_REGSIZE	dwxgmac2.h	/^#define XGMAC_MAC_REGSIZE	/;"	d
XGMAC_MAX_HASH_TABLE	dwxgmac2.h	/^#define XGMAC_MAX_HASH_TABLE	/;"	d
XGMAC_MCSIS	dwxgmac2.h	/^#define XGMAC_MCSIS	/;"	d
XGMAC_MDIO_ADDR	dwxgmac2.h	/^#define XGMAC_MDIO_ADDR	/;"	d
XGMAC_MDIO_C22P	dwxgmac2.h	/^#define XGMAC_MDIO_C22P	/;"	d
XGMAC_MDIO_DATA	dwxgmac2.h	/^#define XGMAC_MDIO_DATA	/;"	d
XGMAC_MECIS	dwxgmac2.h	/^#define XGMAC_MECIS	/;"	d
XGMAC_MEUIS	dwxgmac2.h	/^#define XGMAC_MEUIS	/;"	d
XGMAC_MGKPKTEN	dwxgmac2.h	/^#define XGMAC_MGKPKTEN	/;"	d
XGMAC_MSCIS	dwxgmac2.h	/^#define XGMAC_MSCIS	/;"	d
XGMAC_MSUIS	dwxgmac2.h	/^#define XGMAC_MSUIS	/;"	d
XGMAC_MTL_ECC_CONTROL	dwxgmac2.h	/^#define XGMAC_MTL_ECC_CONTROL	/;"	d
XGMAC_MTL_ECC_INT_ENABLE	dwxgmac2.h	/^#define XGMAC_MTL_ECC_INT_ENABLE	/;"	d
XGMAC_MTL_ECC_INT_STATUS	dwxgmac2.h	/^#define XGMAC_MTL_ECC_INT_STATUS	/;"	d
XGMAC_MTL_EST_CONTROL	dwxgmac2.h	/^#define XGMAC_MTL_EST_CONTROL	/;"	d
XGMAC_MTL_EST_GCL_CONTROL	dwxgmac2.h	/^#define XGMAC_MTL_EST_GCL_CONTROL	/;"	d
XGMAC_MTL_EST_GCL_DATA	dwxgmac2.h	/^#define XGMAC_MTL_EST_GCL_DATA	/;"	d
XGMAC_MTL_INT_STATUS	dwxgmac2.h	/^#define XGMAC_MTL_INT_STATUS	/;"	d
XGMAC_MTL_OPMODE	dwxgmac2.h	/^#define XGMAC_MTL_OPMODE	/;"	d
XGMAC_MTL_QINTEN	dwxgmac2.h	/^#define XGMAC_MTL_QINTEN(/;"	d
XGMAC_MTL_QINT_STATUS	dwxgmac2.h	/^#define XGMAC_MTL_QINT_STATUS(/;"	d
XGMAC_MTL_RXP_CONTROL_STATUS	dwxgmac2.h	/^#define XGMAC_MTL_RXP_CONTROL_STATUS	/;"	d
XGMAC_MTL_RXP_IACC_CTRL_ST	dwxgmac2.h	/^#define XGMAC_MTL_RXP_IACC_CTRL_ST	/;"	d
XGMAC_MTL_RXP_IACC_DATA	dwxgmac2.h	/^#define XGMAC_MTL_RXP_IACC_DATA	/;"	d
XGMAC_MTL_RXQ_DMA_MAP0	dwxgmac2.h	/^#define XGMAC_MTL_RXQ_DMA_MAP0	/;"	d
XGMAC_MTL_RXQ_DMA_MAP1	dwxgmac2.h	/^#define XGMAC_MTL_RXQ_DMA_MAP1	/;"	d
XGMAC_MTL_RXQ_FLOW_CONTROL	dwxgmac2.h	/^#define XGMAC_MTL_RXQ_FLOW_CONTROL(/;"	d
XGMAC_MTL_RXQ_OPMODE	dwxgmac2.h	/^#define XGMAC_MTL_RXQ_OPMODE(/;"	d
XGMAC_MTL_SAFETY_INT_STATUS	dwxgmac2.h	/^#define XGMAC_MTL_SAFETY_INT_STATUS	/;"	d
XGMAC_MTL_TCx_ETS_CONTROL	dwxgmac2.h	/^#define XGMAC_MTL_TCx_ETS_CONTROL(/;"	d
XGMAC_MTL_TCx_HICREDIT	dwxgmac2.h	/^#define XGMAC_MTL_TCx_HICREDIT(/;"	d
XGMAC_MTL_TCx_LOCREDIT	dwxgmac2.h	/^#define XGMAC_MTL_TCx_LOCREDIT(/;"	d
XGMAC_MTL_TCx_QUANTUM_WEIGHT	dwxgmac2.h	/^#define XGMAC_MTL_TCx_QUANTUM_WEIGHT(/;"	d
XGMAC_MTL_TCx_SENDSLOPE	dwxgmac2.h	/^#define XGMAC_MTL_TCx_SENDSLOPE(/;"	d
XGMAC_MTL_TXQ_OPMODE	dwxgmac2.h	/^#define XGMAC_MTL_TXQ_OPMODE(/;"	d
XGMAC_NIE	dwxgmac2.h	/^#define XGMAC_NIE	/;"	d
XGMAC_NIS	dwxgmac2.h	/^#define XGMAC_NIS	/;"	d
XGMAC_NPE	dwxgmac2.h	/^#define XGMAC_NPE	/;"	d
XGMAC_NVE	dwxgmac2.h	/^#define XGMAC_NVE	/;"	d
XGMAC_OB	dwxgmac2.h	/^#define XGMAC_OB	/;"	d
XGMAC_OSP	dwxgmac2.h	/^#define XGMAC_OSP	/;"	d
XGMAC_PACKET_FILTER	dwxgmac2.h	/^#define XGMAC_PACKET_FILTER	/;"	d
XGMAC_PBLx8	dwxgmac2.h	/^#define XGMAC_PBLx8	/;"	d
XGMAC_PLS	dwxgmac2.h	/^#define XGMAC_PLS	/;"	d
XGMAC_PMT	dwxgmac2.h	/^#define XGMAC_PMT	/;"	d
XGMAC_PMTIE	dwxgmac2.h	/^#define XGMAC_PMTIE	/;"	d
XGMAC_PMTIS	dwxgmac2.h	/^#define XGMAC_PMTIS	/;"	d
XGMAC_PPSCMD_START	dwxgmac2.h	/^#define XGMAC_PPSCMD_START	/;"	d
XGMAC_PPSCMD_STOP	dwxgmac2.h	/^#define XGMAC_PPSCMD_STOP	/;"	d
XGMAC_PPSCMDx	dwxgmac2.h	/^#define XGMAC_PPSCMDx(/;"	d
XGMAC_PPSEN0	dwxgmac2.h	/^#define XGMAC_PPSEN0	/;"	d
XGMAC_PPS_CONTROL	dwxgmac2.h	/^#define XGMAC_PPS_CONTROL	/;"	d
XGMAC_PPS_MAXIDX	dwxgmac2.h	/^#define XGMAC_PPS_MAXIDX(/;"	d
XGMAC_PPS_MINIDX	dwxgmac2.h	/^#define XGMAC_PPS_MINIDX(/;"	d
XGMAC_PPSx_INTERVAL	dwxgmac2.h	/^#define XGMAC_PPSx_INTERVAL(/;"	d
XGMAC_PPSx_MASK	dwxgmac2.h	/^#define XGMAC_PPSx_MASK(/;"	d
XGMAC_PPSx_TARGET_TIME_NSEC	dwxgmac2.h	/^#define XGMAC_PPSx_TARGET_TIME_NSEC(/;"	d
XGMAC_PPSx_TARGET_TIME_SEC	dwxgmac2.h	/^#define XGMAC_PPSx_TARGET_TIME_SEC(/;"	d
XGMAC_PPSx_WIDTH	dwxgmac2.h	/^#define XGMAC_PPSx_WIDTH(/;"	d
XGMAC_PRTYEN	dwxgmac2.h	/^#define XGMAC_PRTYEN	/;"	d
XGMAC_PSRQ	dwxgmac2.h	/^#define XGMAC_PSRQ(/;"	d
XGMAC_PSRQ_SHIFT	dwxgmac2.h	/^#define XGMAC_PSRQ_SHIFT(/;"	d
XGMAC_PSTC	dwxgmac2.h	/^#define XGMAC_PSTC(/;"	d
XGMAC_PSTC_SHIFT	dwxgmac2.h	/^#define XGMAC_PSTC_SHIFT(/;"	d
XGMAC_PT	dwxgmac2.h	/^#define XGMAC_PT	/;"	d
XGMAC_PTOV	dwxgmac2.h	/^#define XGMAC_PTOV	/;"	d
XGMAC_PTOV_SHIFT	dwxgmac2.h	/^#define XGMAC_PTOV_SHIFT	/;"	d
XGMAC_PT_SHIFT	dwxgmac2.h	/^#define XGMAC_PT_SHIFT	/;"	d
XGMAC_PWRDWN	dwxgmac2.h	/^#define XGMAC_PWRDWN	/;"	d
XGMAC_Q2TCMAP	dwxgmac2.h	/^#define XGMAC_Q2TCMAP	/;"	d
XGMAC_Q2TCMAP_SHIFT	dwxgmac2.h	/^#define XGMAC_Q2TCMAP_SHIFT	/;"	d
XGMAC_QDDMACH	dwxgmac2.h	/^#define XGMAC_QDDMACH	/;"	d
XGMAC_QxMDMACH	dwxgmac2.h	/^#define XGMAC_QxMDMACH(/;"	d
XGMAC_QxMDMACH_SHIFT	dwxgmac2.h	/^#define XGMAC_QxMDMACH_SHIFT(/;"	d
XGMAC_Qx_TX_FLOW_CTRL	dwxgmac2.h	/^#define XGMAC_Qx_TX_FLOW_CTRL(/;"	d
XGMAC_RAA	dwxgmac2.h	/^#define XGMAC_RAA	/;"	d
XGMAC_RBSZ	dwxgmac2.h	/^#define XGMAC_RBSZ	/;"	d
XGMAC_RBSZ_SHIFT	dwxgmac2.h	/^#define XGMAC_RBSZ_SHIFT	/;"	d
XGMAC_RBU	dwxgmac2.h	/^#define XGMAC_RBU	/;"	d
XGMAC_RBUE	dwxgmac2.h	/^#define XGMAC_RBUE	/;"	d
XGMAC_RDES2_HL	dwxgmac2.h	/^#define XGMAC_RDES2_HL	/;"	d
XGMAC_RDES3_CDA	dwxgmac2.h	/^#define XGMAC_RDES3_CDA	/;"	d
XGMAC_RDES3_CTXT	dwxgmac2.h	/^#define XGMAC_RDES3_CTXT	/;"	d
XGMAC_RDES3_ES	dwxgmac2.h	/^#define XGMAC_RDES3_ES	/;"	d
XGMAC_RDES3_IOC	dwxgmac2.h	/^#define XGMAC_RDES3_IOC	/;"	d
XGMAC_RDES3_L34T	dwxgmac2.h	/^#define XGMAC_RDES3_L34T	/;"	d
XGMAC_RDES3_L34T_SHIFT	dwxgmac2.h	/^#define XGMAC_RDES3_L34T_SHIFT	/;"	d
XGMAC_RDES3_LD	dwxgmac2.h	/^#define XGMAC_RDES3_LD	/;"	d
XGMAC_RDES3_OWN	dwxgmac2.h	/^#define XGMAC_RDES3_OWN	/;"	d
XGMAC_RDES3_PL	dwxgmac2.h	/^#define XGMAC_RDES3_PL	/;"	d
XGMAC_RDES3_RSV	dwxgmac2.h	/^#define XGMAC_RDES3_RSV	/;"	d
XGMAC_RDES3_TSA	dwxgmac2.h	/^#define XGMAC_RDES3_TSA	/;"	d
XGMAC_RDES3_TSD	dwxgmac2.h	/^#define XGMAC_RDES3_TSD	/;"	d
XGMAC_RDPS	dwxgmac2.h	/^#define XGMAC_RDPS	/;"	d
XGMAC_RD_OSR_LMT	dwxgmac2.h	/^#define XGMAC_RD_OSR_LMT	/;"	d
XGMAC_RD_OSR_LMT_SHIFT	dwxgmac2.h	/^#define XGMAC_RD_OSR_LMT_SHIFT	/;"	d
XGMAC_REGSIZE	dwxgmac2.h	/^#define XGMAC_REGSIZE	/;"	d
XGMAC_RFA	dwxgmac2.h	/^#define XGMAC_RFA	/;"	d
XGMAC_RFA_SHIFT	dwxgmac2.h	/^#define XGMAC_RFA_SHIFT	/;"	d
XGMAC_RFD	dwxgmac2.h	/^#define XGMAC_RFD	/;"	d
XGMAC_RFD_SHIFT	dwxgmac2.h	/^#define XGMAC_RFD_SHIFT	/;"	d
XGMAC_RFE	dwxgmac2.h	/^#define XGMAC_RFE	/;"	d
XGMAC_RI	dwxgmac2.h	/^#define XGMAC_RI	/;"	d
XGMAC_RIE	dwxgmac2.h	/^#define XGMAC_RIE	/;"	d
XGMAC_RLPIEN	dwxgmac2.h	/^#define XGMAC_RLPIEN	/;"	d
XGMAC_RLPIEX	dwxgmac2.h	/^#define XGMAC_RLPIEX	/;"	d
XGMAC_RPCEIE	dwxgmac2.h	/^#define XGMAC_RPCEIE	/;"	d
XGMAC_RQ	dwxgmac2.h	/^#define XGMAC_RQ	/;"	d
XGMAC_RQS	dwxgmac2.h	/^#define XGMAC_RQS	/;"	d
XGMAC_RQS_SHIFT	dwxgmac2.h	/^#define XGMAC_RQS_SHIFT	/;"	d
XGMAC_RQ_SHIFT	dwxgmac2.h	/^#define XGMAC_RQ_SHIFT	/;"	d
XGMAC_RSF	dwxgmac2.h	/^#define XGMAC_RSF	/;"	d
XGMAC_RSSE	dwxgmac2.h	/^#define XGMAC_RSSE	/;"	d
XGMAC_RSSIA_SHIFT	dwxgmac2.h	/^#define XGMAC_RSSIA_SHIFT	/;"	d
XGMAC_RSS_ADDR	dwxgmac2.h	/^#define XGMAC_RSS_ADDR	/;"	d
XGMAC_RSS_CTRL	dwxgmac2.h	/^#define XGMAC_RSS_CTRL	/;"	d
XGMAC_RSS_DATA	dwxgmac2.h	/^#define XGMAC_RSS_DATA	/;"	d
XGMAC_RTC	dwxgmac2.h	/^#define XGMAC_RTC	/;"	d
XGMAC_RTC_SHIFT	dwxgmac2.h	/^#define XGMAC_RTC_SHIFT	/;"	d
XGMAC_RWKPKTEN	dwxgmac2.h	/^#define XGMAC_RWKPKTEN	/;"	d
XGMAC_RWT	dwxgmac2.h	/^#define XGMAC_RWT	/;"	d
XGMAC_RXCEIE	dwxgmac2.h	/^#define XGMAC_RXCEIE	/;"	d
XGMAC_RXOIE	dwxgmac2.h	/^#define XGMAC_RXOIE	/;"	d
XGMAC_RXOVFIS	dwxgmac2.h	/^#define XGMAC_RXOVFIS	/;"	d
XGMAC_RXPI	dwxgmac2.h	/^#define XGMAC_RXPI	/;"	d
XGMAC_RXQEN	dwxgmac2.h	/^#define XGMAC_RXQEN(/;"	d
XGMAC_RXQEN_SHIFT	dwxgmac2.h	/^#define XGMAC_RXQEN_SHIFT(/;"	d
XGMAC_RXQ_CTRL0	dwxgmac2.h	/^#define XGMAC_RXQ_CTRL0	/;"	d
XGMAC_RXQ_CTRL1	dwxgmac2.h	/^#define XGMAC_RXQ_CTRL1	/;"	d
XGMAC_RXQ_CTRL2	dwxgmac2.h	/^#define XGMAC_RXQ_CTRL2	/;"	d
XGMAC_RXQ_CTRL3	dwxgmac2.h	/^#define XGMAC_RXQ_CTRL3	/;"	d
XGMAC_RXST	dwxgmac2.h	/^#define XGMAC_RXST	/;"	d
XGMAC_RX_CONFIG	dwxgmac2.h	/^#define XGMAC_RX_CONFIG	/;"	d
XGMAC_RX_EDMA_CTRL	dwxgmac2.h	/^#define XGMAC_RX_EDMA_CTRL	/;"	d
XGMAC_RX_FLOW_CTRL	dwxgmac2.h	/^#define XGMAC_RX_FLOW_CTRL	/;"	d
XGMAC_RxPBL	dwxgmac2.h	/^#define XGMAC_RxPBL	/;"	d
XGMAC_RxPBL_SHIFT	dwxgmac2.h	/^#define XGMAC_RxPBL_SHIFT	/;"	d
XGMAC_SP	dwxgmac2.h	/^#define XGMAC_SP	/;"	d
XGMAC_SPH	dwxgmac2.h	/^#define XGMAC_SPH	/;"	d
XGMAC_SRWO	dwxgmac2.h	/^#define XGMAC_SRWO	/;"	d
XGMAC_SSWL	dwxgmac2.h	/^#define XGMAC_SSWL	/;"	d
XGMAC_STARTBUSY	dwxgmac2.h	/^#define XGMAC_STARTBUSY	/;"	d
XGMAC_SWR	dwxgmac2.h	/^#define XGMAC_SWR	/;"	d
XGMAC_TBU	dwxgmac2.h	/^#define XGMAC_TBU	/;"	d
XGMAC_TBUE	dwxgmac2.h	/^#define XGMAC_TBUE	/;"	d
XGMAC_TCEIE	dwxgmac2.h	/^#define XGMAC_TCEIE	/;"	d
XGMAC_TCP4TE	dwxgmac2.h	/^#define XGMAC_TCP4TE	/;"	d
XGMAC_TC_PRTY_MAP0	dwxgmac2.h	/^#define XGMAC_TC_PRTY_MAP0	/;"	d
XGMAC_TC_PRTY_MAP1	dwxgmac2.h	/^#define XGMAC_TC_PRTY_MAP1	/;"	d
XGMAC_TDES0_LT	dwxgmac2.h	/^#define XGMAC_TDES0_LT	/;"	d
XGMAC_TDES0_LTV	dwxgmac2.h	/^#define XGMAC_TDES0_LTV	/;"	d
XGMAC_TDES1_LT	dwxgmac2.h	/^#define XGMAC_TDES1_LT	/;"	d
XGMAC_TDES2_B1L	dwxgmac2.h	/^#define XGMAC_TDES2_B1L	/;"	d
XGMAC_TDES2_B2L	dwxgmac2.h	/^#define XGMAC_TDES2_B2L	/;"	d
XGMAC_TDES2_B2L_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES2_B2L_SHIFT	/;"	d
XGMAC_TDES2_IOC	dwxgmac2.h	/^#define XGMAC_TDES2_IOC	/;"	d
XGMAC_TDES2_IVT	dwxgmac2.h	/^#define XGMAC_TDES2_IVT	/;"	d
XGMAC_TDES2_IVT_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES2_IVT_SHIFT	/;"	d
XGMAC_TDES2_TTSE	dwxgmac2.h	/^#define XGMAC_TDES2_TTSE	/;"	d
XGMAC_TDES2_VTIR	dwxgmac2.h	/^#define XGMAC_TDES2_VTIR	/;"	d
XGMAC_TDES2_VTIR_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES2_VTIR_SHIFT	/;"	d
XGMAC_TDES3_CIC	dwxgmac2.h	/^#define XGMAC_TDES3_CIC	/;"	d
XGMAC_TDES3_CIC_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES3_CIC_SHIFT	/;"	d
XGMAC_TDES3_CPC	dwxgmac2.h	/^#define XGMAC_TDES3_CPC	/;"	d
XGMAC_TDES3_CPC_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES3_CPC_SHIFT	/;"	d
XGMAC_TDES3_CTXT	dwxgmac2.h	/^#define XGMAC_TDES3_CTXT	/;"	d
XGMAC_TDES3_FD	dwxgmac2.h	/^#define XGMAC_TDES3_FD	/;"	d
XGMAC_TDES3_FL	dwxgmac2.h	/^#define XGMAC_TDES3_FL	/;"	d
XGMAC_TDES3_IVLTV	dwxgmac2.h	/^#define XGMAC_TDES3_IVLTV	/;"	d
XGMAC_TDES3_IVTIR	dwxgmac2.h	/^#define XGMAC_TDES3_IVTIR	/;"	d
XGMAC_TDES3_IVTIR_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES3_IVTIR_SHIFT	/;"	d
XGMAC_TDES3_LD	dwxgmac2.h	/^#define XGMAC_TDES3_LD	/;"	d
XGMAC_TDES3_OWN	dwxgmac2.h	/^#define XGMAC_TDES3_OWN	/;"	d
XGMAC_TDES3_SAIC	dwxgmac2.h	/^#define XGMAC_TDES3_SAIC	/;"	d
XGMAC_TDES3_SAIC_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES3_SAIC_SHIFT	/;"	d
XGMAC_TDES3_TBSV	dwxgmac2.h	/^#define XGMAC_TDES3_TBSV	/;"	d
XGMAC_TDES3_TCMSSV	dwxgmac2.h	/^#define XGMAC_TDES3_TCMSSV	/;"	d
XGMAC_TDES3_THL	dwxgmac2.h	/^#define XGMAC_TDES3_THL	/;"	d
XGMAC_TDES3_THL_SHIFT	dwxgmac2.h	/^#define XGMAC_TDES3_THL_SHIFT	/;"	d
XGMAC_TDES3_TPL	dwxgmac2.h	/^#define XGMAC_TDES3_TPL	/;"	d
XGMAC_TDES3_TSE	dwxgmac2.h	/^#define XGMAC_TDES3_TSE	/;"	d
XGMAC_TDES3_VLTV	dwxgmac2.h	/^#define XGMAC_TDES3_VLTV	/;"	d
XGMAC_TDES3_VT	dwxgmac2.h	/^#define XGMAC_TDES3_VT	/;"	d
XGMAC_TDPS	dwxgmac2.h	/^#define XGMAC_TDPS	/;"	d
XGMAC_TER	dwxgmac2.h	/^#define XGMAC_TER	/;"	d
XGMAC_TFE	dwxgmac2.h	/^#define XGMAC_TFE	/;"	d
XGMAC_TI	dwxgmac2.h	/^#define XGMAC_TI	/;"	d
XGMAC_TIE	dwxgmac2.h	/^#define XGMAC_TIE	/;"	d
XGMAC_TIMESTAMP_STATUS	dwxgmac2.h	/^#define XGMAC_TIMESTAMP_STATUS	/;"	d
XGMAC_TLPIEN	dwxgmac2.h	/^#define XGMAC_TLPIEN	/;"	d
XGMAC_TLPIEX	dwxgmac2.h	/^#define XGMAC_TLPIEX	/;"	d
XGMAC_TMOUTEN	dwxgmac2.h	/^#define XGMAC_TMOUTEN	/;"	d
XGMAC_TPS	dwxgmac2.h	/^#define XGMAC_TPS	/;"	d
XGMAC_TQS	dwxgmac2.h	/^#define XGMAC_TQS	/;"	d
XGMAC_TQS_SHIFT	dwxgmac2.h	/^#define XGMAC_TQS_SHIFT	/;"	d
XGMAC_TRGTBUSY0	dwxgmac2.h	/^#define XGMAC_TRGTBUSY0	/;"	d
XGMAC_TRGTMODSELx	dwxgmac2.h	/^#define XGMAC_TRGTMODSELx(/;"	d
XGMAC_TSA	dwxgmac2.h	/^#define XGMAC_TSA	/;"	d
XGMAC_TSE	dwxgmac2.h	/^#define XGMAC_TSE	/;"	d
XGMAC_TSF	dwxgmac2.h	/^#define XGMAC_TSF	/;"	d
XGMAC_TSIE	dwxgmac2.h	/^#define XGMAC_TSIE	/;"	d
XGMAC_TT	dwxgmac2.h	/^#define XGMAC_TT	/;"	d
XGMAC_TTC	dwxgmac2.h	/^#define XGMAC_TTC	/;"	d
XGMAC_TTC_SHIFT	dwxgmac2.h	/^#define XGMAC_TTC_SHIFT	/;"	d
XGMAC_TXCEIE	dwxgmac2.h	/^#define XGMAC_TXCEIE	/;"	d
XGMAC_TXCGE	dwxgmac2.h	/^#define XGMAC_TXCGE	/;"	d
XGMAC_TXQEN	dwxgmac2.h	/^#define XGMAC_TXQEN	/;"	d
XGMAC_TXQEN_SHIFT	dwxgmac2.h	/^#define XGMAC_TXQEN_SHIFT	/;"	d
XGMAC_TXST	dwxgmac2.h	/^#define XGMAC_TXST	/;"	d
XGMAC_TXTIMESTAMP_NSEC	dwxgmac2.h	/^#define XGMAC_TXTIMESTAMP_NSEC	/;"	d
XGMAC_TXTIMESTAMP_SEC	dwxgmac2.h	/^#define XGMAC_TXTIMESTAMP_SEC	/;"	d
XGMAC_TXTSC	dwxgmac2.h	/^#define XGMAC_TXTSC	/;"	d
XGMAC_TXTSSTSLO	dwxgmac2.h	/^#define XGMAC_TXTSSTSLO	/;"	d
XGMAC_TXUNFIS	dwxgmac2.h	/^#define XGMAC_TXUNFIS	/;"	d
XGMAC_TX_CONFIG	dwxgmac2.h	/^#define XGMAC_TX_CONFIG	/;"	d
XGMAC_TX_EDMA_CTRL	dwxgmac2.h	/^#define XGMAC_TX_EDMA_CTRL	/;"	d
XGMAC_TxPBL	dwxgmac2.h	/^#define XGMAC_TxPBL	/;"	d
XGMAC_TxPBL_SHIFT	dwxgmac2.h	/^#define XGMAC_TxPBL_SHIFT	/;"	d
XGMAC_UDP4TE	dwxgmac2.h	/^#define XGMAC_UDP4TE	/;"	d
XGMAC_UNDEF	dwxgmac2.h	/^#define XGMAC_UNDEF	/;"	d
XGMAC_VLAN_CSVL	dwxgmac2.h	/^#define XGMAC_VLAN_CSVL	/;"	d
XGMAC_VLAN_DOVLTC	dwxgmac2.h	/^#define XGMAC_VLAN_DOVLTC	/;"	d
XGMAC_VLAN_EDVLP	dwxgmac2.h	/^#define XGMAC_VLAN_EDVLP	/;"	d
XGMAC_VLAN_ESVL	dwxgmac2.h	/^#define XGMAC_VLAN_ESVL	/;"	d
XGMAC_VLAN_ETV	dwxgmac2.h	/^#define XGMAC_VLAN_ETV	/;"	d
XGMAC_VLAN_HASH_TABLE	dwxgmac2.h	/^#define XGMAC_VLAN_HASH_TABLE	/;"	d
XGMAC_VLAN_INCL	dwxgmac2.h	/^#define XGMAC_VLAN_INCL	/;"	d
XGMAC_VLAN_TAG	dwxgmac2.h	/^#define XGMAC_VLAN_TAG	/;"	d
XGMAC_VLAN_VID	dwxgmac2.h	/^#define XGMAC_VLAN_VID	/;"	d
XGMAC_VLAN_VLC	dwxgmac2.h	/^#define XGMAC_VLAN_VLC	/;"	d
XGMAC_VLAN_VLC_SHIFT	dwxgmac2.h	/^#define XGMAC_VLAN_VLC_SHIFT	/;"	d
XGMAC_VLAN_VLTI	dwxgmac2.h	/^#define XGMAC_VLAN_VLTI	/;"	d
XGMAC_VLAN_VTHM	dwxgmac2.h	/^#define XGMAC_VLAN_VTHM	/;"	d
XGMAC_WFQ	dwxgmac2.h	/^#define XGMAC_WFQ	/;"	d
XGMAC_WRR	dwxgmac2.h	/^#define XGMAC_WRR	/;"	d
XGMAC_WRRDN	dwxgmac2.h	/^#define XGMAC_WRRDN	/;"	d
XGMAC_WR_OSR_LMT	dwxgmac2.h	/^#define XGMAC_WR_OSR_LMT	/;"	d
XGMAC_WR_OSR_LMT_SHIFT	dwxgmac2.h	/^#define XGMAC_WR_OSR_LMT_SHIFT	/;"	d
XGMAC_XB	dwxgmac2.h	/^#define XGMAC_XB	/;"	d
XLGMAC_CONFIG_SS	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS	/;"	d
XLGMAC_CONFIG_SS_1000	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_1000	/;"	d
XLGMAC_CONFIG_SS_100G	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_100G	/;"	d
XLGMAC_CONFIG_SS_10G	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_10G	/;"	d
XLGMAC_CONFIG_SS_2500	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_2500	/;"	d
XLGMAC_CONFIG_SS_25G	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_25G	/;"	d
XLGMAC_CONFIG_SS_40G	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_40G	/;"	d
XLGMAC_CONFIG_SS_50G	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_50G	/;"	d
XLGMAC_CONFIG_SS_SHIFT	dwxlgmac2.h	/^#define XLGMAC_CONFIG_SS_SHIFT	/;"	d
XLGMAC_RXQ_ENABLE_CTRL0	dwxlgmac2.h	/^#define XLGMAC_RXQ_ENABLE_CTRL0	/;"	d
XMGAC_L3_ADDR3	dwxgmac2.h	/^#define XMGAC_L3_ADDR3	/;"	d
__COMMON_H__	common.h	/^#define __COMMON_H__$/;"	d
__DESCS_H__	descs.h	/^#define __DESCS_H__$/;"	d
__DESC_COM_H__	descs_com.h	/^#define __DESC_COM_H__$/;"	d
__DWMAC1000_H__	dwmac1000.h	/^#define __DWMAC1000_H__$/;"	d
__DWMAC100_H__	dwmac100.h	/^#define __DWMAC100_H__$/;"	d
__DWMAC4_DESCS_H__	dwmac4_descs.h	/^#define __DWMAC4_DESCS_H__$/;"	d
__DWMAC4_DMA_H__	dwmac4_dma.h	/^#define __DWMAC4_DMA_H__$/;"	d
__DWMAC4_H__	dwmac4.h	/^#define __DWMAC4_H__$/;"	d
__DWMAC5_H__	dwmac5.h	/^#define __DWMAC5_H__$/;"	d
__DWMAC_DMA_H__	dwmac_dma.h	/^#define __DWMAC_DMA_H__$/;"	d
__DWMAC_INTEL_H__	dwmac-intel.h	/^#define __DWMAC_INTEL_H__$/;"	d
__MMC_H__	mmc.h	/^#define __MMC_H__$/;"	d
__STMMAC_DWXGMAC2_H__	dwxgmac2.h	/^#define __STMMAC_DWXGMAC2_H__$/;"	d
__STMMAC_DWXLGMAC2_H__	dwxlgmac2.h	/^#define __STMMAC_DWXLGMAC2_H__$/;"	d
__STMMAC_HWIF_H__	hwif.h	/^#define __STMMAC_HWIF_H__$/;"	d
__STMMAC_H__	stmmac.h	/^#define __STMMAC_H__$/;"	d
__STMMAC_PCS_H__	stmmac_pcs.h	/^#define __STMMAC_PCS_H__$/;"	d
__STMMAC_PLATFORM_H__	stmmac_platform.h	/^#define __STMMAC_PLATFORM_H__$/;"	d
__STMMAC_PTP_H__	stmmac_ptp.h	/^#define	__STMMAC_PTP_H__$/;"	d
__TSE_PCS_H__	altr_tse_pcs.h	/^#define __TSE_PCS_H__$/;"	d
____cacheline_aligned	common.h	/^	unsigned long tx_underflow ____cacheline_aligned;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long tx_underflow
____cacheline_aligned_in_smp	stmmac.h	/^	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;$/;"	m	struct:stmmac_rx_queue	typeref:struct:dma_desc * dma_rx
____cacheline_aligned_in_smp	stmmac.h	/^	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;$/;"	m	struct:stmmac_tx_queue	typeref:struct:dma_extended_desc * dma_etx
____cacheline_aligned_in_smp	stmmac.h	/^	struct napi_struct rx_napi ____cacheline_aligned_in_smp;$/;"	m	struct:stmmac_channel	typeref:struct:napi_struct rx_napi
____cacheline_aligned_in_smp	stmmac.h	/^	struct napi_struct tx_napi ____cacheline_aligned_in_smp;$/;"	m	struct:stmmac_channel	typeref:struct:napi_struct tx_napi
____cacheline_aligned_in_smp	stmmac.h	/^	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_extra_stats xstats
__anon3897d81f0103	dwmac-sti.c	/^enum {$/;"	g	file:
__anon3fde68840108	common.h	/^	struct {$/;"	s	struct:mac_link
__anon3fde68840208	common.h	/^	struct {$/;"	s	struct:mac_link
__anon81ae60170108	stmmac_selftests.c	/^	struct {$/;"	s	function:__stmmac_test_l4filt	file:
__anon81ae60170208	stmmac_selftests.c	/^	struct {$/;"	s	function:__stmmac_test_l4filt	file:
__anon84d70a400108	stmmac.h	/^	struct {$/;"	s	struct:stmmac_rx_queue
__anon84d70a400208	stmmac.h	/^	struct {$/;"	s	struct:stmmac_tc_entry
__anonf294d2f10108	stmmac_tc.c	/^static struct {$/;"	s	file:
__packed	stmmac_selftests.c	/^} __packed;$/;"	v	typeref:struct:stmmachdr
__stmmac_test_dvlanfilt	stmmac_selftests.c	/^static int __stmmac_test_dvlanfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
__stmmac_test_jumbo	stmmac_selftests.c	/^static int __stmmac_test_jumbo(struct stmmac_priv *priv, u16 queue)$/;"	f	typeref:typename:int	file:
__stmmac_test_l3filt	stmmac_selftests.c	/^static int __stmmac_test_l3filt(struct stmmac_priv *priv, u32 dst, u32 src,$/;"	f	typeref:typename:int	file:
__stmmac_test_l4filt	stmmac_selftests.c	/^static int __stmmac_test_l4filt(struct stmmac_priv *priv, u32 dst, u32 src,$/;"	f	typeref:typename:int	file:
__stmmac_test_loopback	stmmac_selftests.c	/^static int __stmmac_test_loopback(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
__stmmac_test_vlanfilt	stmmac_selftests.c	/^static int __stmmac_test_vlanfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
_dwmac4_dump_dma_regs	dwmac4_dma.c	/^static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,$/;"	f	typeref:typename:void	file:
aclk_mac	dwmac-rk.c	/^	struct clk *aclk_mac;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
act_full_minus_1	dwmac1000.h	/^	act_full_minus_1 = 0x00800000,$/;"	e	enum:rfa
act_full_minus_2	dwmac1000.h	/^	act_full_minus_2 = 0x00800200,$/;"	e	enum:rfa
act_full_minus_3	dwmac1000.h	/^	act_full_minus_3 = 0x00800400,$/;"	e	enum:rfa
act_full_minus_4	dwmac1000.h	/^	act_full_minus_4 = 0x00800600,$/;"	e	enum:rfa
action	stmmac.h	/^	unsigned long action;$/;"	m	struct:stmmac_flow_entry	typeref:typename:unsigned long
active_vlans	stmmac.h	/^	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];$/;"	m	struct:stmmac_priv	typeref:typename:unsigned long[]
add_hw_vlan_rx_fltr	hwif.h	/^	int (*add_hw_vlan_rx_fltr)(struct net_device *dev,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct net_device * dev,struct mac_device_info * hw,__be16 proto,u16 vid)
addr	common.h	/^	unsigned int addr;	\/* MII Address *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
addr	stmmac.h	/^	dma_addr_t addr;$/;"	m	struct:stmmac_rx_buffer	typeref:typename:dma_addr_t
addr	stmmac.h	/^	void __iomem *addr;$/;"	m	struct:stmmac_resources	typeref:typename:void __iomem *
addr64	common.h	/^	unsigned int addr64;$/;"	m	struct:dma_features	typeref:typename:unsigned int
addr_mask	common.h	/^	unsigned int addr_mask;		\/* MII address mask *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
addr_shift	common.h	/^	unsigned int addr_shift;	\/* MII address shift *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
addr_width	dwmac-imx.c	/^	u32 addr_width;$/;"	m	struct:imx_dwmac_ops	typeref:typename:u32	file:
adjust_systime	hwif.h	/^	int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:int (*)(void __iomem * ioaddr,u32 sec,u32 nsec,int add_sub,int gmac4)
adjust_systime	stmmac_hwtstamp.c	/^static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,$/;"	f	typeref:typename:int	file:
adv_ts	stmmac.h	/^	u32 adv_ts;$/;"	m	struct:stmmac_priv	typeref:typename:u32
af	stmmac.h	/^		u8 af:1;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8:1
alloc_dma_desc_resources	stmmac_main.c	/^static int alloc_dma_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
alloc_dma_rx_desc_resources	stmmac_main.c	/^static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
alloc_dma_tx_desc_resources	stmmac_main.c	/^static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
anarion_config_dt	dwmac-anarion.c	/^static struct anarion_gmac *anarion_config_dt(struct platform_device *pdev)$/;"	f	typeref:struct:anarion_gmac *	file:
anarion_dwmac_driver	dwmac-anarion.c	/^static struct platform_driver anarion_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
anarion_dwmac_match	dwmac-anarion.c	/^static const struct of_device_id anarion_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
anarion_dwmac_probe	dwmac-anarion.c	/^static int anarion_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
anarion_gmac	dwmac-anarion.c	/^struct anarion_gmac {$/;"	s	file:
anarion_gmac_exit	dwmac-anarion.c	/^static void anarion_gmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
anarion_gmac_init	dwmac-anarion.c	/^static int anarion_gmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
aneg_link_timer	altr_tse_pcs.h	/^	struct timer_list aneg_link_timer;$/;"	m	struct:tse_pcs	typeref:struct:timer_list
aneg_link_timer_callback	altr_tse_pcs.c	/^static void aneg_link_timer_callback(struct timer_list *t)$/;"	f	typeref:typename:void	file:
arpoffsel	common.h	/^	unsigned int arpoffsel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
asp	common.h	/^	unsigned int asp;$/;"	m	struct:dma_features	typeref:typename:unsigned int
atime_stamp	common.h	/^	unsigned int atime_stamp;$/;"	m	struct:dma_features	typeref:typename:unsigned int
auto_nego_timer_callback	altr_tse_pcs.c	/^static void auto_nego_timer_callback(struct tse_pcs *pcs)$/;"	f	typeref:typename:void	file:
autoneg	altr_tse_pcs.h	/^	int autoneg;$/;"	m	struct:tse_pcs	typeref:typename:int
av	common.h	/^	unsigned int av;$/;"	m	struct:dma_features	typeref:typename:unsigned int
av_pkt_rcvd	common.h	/^	unsigned long av_pkt_rcvd;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
av_tagged_pkt_rcvd	common.h	/^	unsigned long av_tagged_pkt_rcvd;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
available	stmmac.h	/^	bool available;$/;"	m	struct:stmmac_pps_cfg	typeref:typename:bool
axi	hwif.h	/^	void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_axi * axi)
basic	descs.h	/^	struct dma_desc basic;	\/* Basic descriptors *\/$/;"	m	struct:dma_extended_desc	typeref:struct:dma_desc
basic	descs.h	/^	struct dma_desc basic;$/;"	m	struct:dma_edesc	typeref:struct:dma_desc
bkey	stmmac_selftests.c	/^		struct flow_dissector_key_basic bkey;$/;"	m	struct:__stmmac_test_l4filt::__anon81ae60170108	typeref:struct:flow_dissector_key_basic	file:
bmask	stmmac_selftests.c	/^		struct flow_dissector_key_basic bmask;$/;"	m	struct:__stmmac_test_l4filt::__anon81ae60170208	typeref:struct:flow_dissector_key_basic	file:
buf	stmmac.h	/^	dma_addr_t buf;$/;"	m	struct:stmmac_tx_info	typeref:typename:dma_addr_t
buf_pool	stmmac.h	/^	struct stmmac_rx_buffer *buf_pool;$/;"	m	struct:stmmac_rx_queue	typeref:struct:stmmac_rx_buffer *
buf_sz	stmmac_main.c	/^static int buf_sz = DEFAULT_BUFSIZE;$/;"	v	typeref:typename:int	file:
chain_mode	stmmac.h	/^	unsigned int chain_mode;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
chain_mode	stmmac_main.c	/^static unsigned int chain_mode;$/;"	v	typeref:typename:unsigned int	file:
chain_mode_ops	chain_mode.c	/^const struct stmmac_mode_ops chain_mode_ops = {$/;"	v	typeref:typename:const struct stmmac_mode_ops
channel	stmmac.h	/^	struct stmmac_channel channel[STMMAC_CH_MAX];$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_channel[]
clean_desc3	chain_mode.c	/^static void clean_desc3(void *priv_ptr, struct dma_desc *p)$/;"	f	typeref:typename:void	file:
clean_desc3	hwif.h	/^	void (*clean_desc3) (void *priv, struct dma_desc *p);$/;"	m	struct:stmmac_mode_ops	typeref:typename:void (*)(void * priv,struct dma_desc * p)
clean_desc3	ring_mode.c	/^static void clean_desc3(void *priv_ptr, struct dma_desc *p)$/;"	f	typeref:typename:void	file:
clear	hwif.h	/^	void (*clear)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p)
clk	dwmac-oxnas.c	/^	struct clk	*clk;$/;"	m	struct:oxnas_dwmac	typeref:struct:clk *	file:
clk	dwmac-sti.c	/^	struct clk *clk;	\/* PHY clock *\/$/;"	m	struct:sti_dwmac	typeref:struct:clk *	file:
clk_csr	stmmac.h	/^	int clk_csr;$/;"	m	struct:stmmac_priv	typeref:typename:int
clk_csr_mask	common.h	/^	unsigned int clk_csr_mask;$/;"	m	struct:mii_regs	typeref:typename:unsigned int
clk_csr_shift	common.h	/^	unsigned int clk_csr_shift;$/;"	m	struct:mii_regs	typeref:typename:unsigned int
clk_enabled	dwmac-rk.c	/^	bool clk_enabled;$/;"	m	struct:rk_priv_data	typeref:typename:bool	file:
clk_enabled	dwmac-sunxi.c	/^	int clk_enabled;$/;"	m	struct:sunxi_priv_data	typeref:typename:int	file:
clk_eth_ck	dwmac-stm32.c	/^	struct clk *clk_eth_ck;$/;"	m	struct:stm32_dwmac	typeref:struct:clk *	file:
clk_ethstp	dwmac-stm32.c	/^	struct clk *clk_ethstp;$/;"	m	struct:stm32_dwmac	typeref:struct:clk *	file:
clk_list	dwmac-mediatek.c	/^	const char * const *clk_list;$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:const char * const *	file:
clk_mac	dwmac-rk.c	/^	struct clk *clk_mac;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
clk_mac_ref	dwmac-rk.c	/^	struct clk *clk_mac_ref;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
clk_mac_refout	dwmac-rk.c	/^	struct clk *clk_mac_refout;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
clk_mac_speed	dwmac-rk.c	/^	struct clk *clk_mac_speed;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
clk_master	dwmac-dwc-qos-eth.c	/^	struct clk *clk_master;$/;"	m	struct:tegra_eqos	typeref:struct:clk *	file:
clk_mem	dwmac-imx.c	/^	struct clk *clk_mem;$/;"	m	struct:imx_priv_data	typeref:struct:clk *	file:
clk_phy	dwmac-rk.c	/^	struct clk *clk_phy;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
clk_prepare	dwmac-stm32.c	/^	int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);$/;"	m	struct:stm32_ops	typeref:typename:int (*)(struct stm32_dwmac * dwmac,bool prepare)	file:
clk_rx	dwmac-dwc-qos-eth.c	/^	struct clk *clk_rx;$/;"	m	struct:tegra_eqos	typeref:struct:clk *	file:
clk_rx	dwmac-stm32.c	/^	struct clk *clk_rx;$/;"	m	struct:stm32_dwmac	typeref:struct:clk *	file:
clk_sel_reg	dwmac-sti.c	/^	int clk_sel_reg;	\/* GMAC ext clk selection register *\/$/;"	m	struct:sti_dwmac	typeref:typename:int	file:
clk_slave	dwmac-dwc-qos-eth.c	/^	struct clk *clk_slave;$/;"	m	struct:tegra_eqos	typeref:struct:clk *	file:
clk_tx	dwmac-dwc-qos-eth.c	/^	struct clk *clk_tx;$/;"	m	struct:tegra_eqos	typeref:struct:clk *	file:
clk_tx	dwmac-imx.c	/^	struct clk *clk_tx;$/;"	m	struct:imx_priv_data	typeref:struct:clk *	file:
clk_tx	dwmac-stm32.c	/^	struct clk *clk_tx;$/;"	m	struct:stm32_dwmac	typeref:struct:clk *	file:
clks	dwmac-mediatek.c	/^	struct clk_bulk_data *clks;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:struct:clk_bulk_data *	file:
clock_input	dwmac-rk.c	/^	bool clock_input;$/;"	m	struct:rk_priv_data	typeref:typename:bool	file:
common_default_data	dwmac-intel.c	/^static void common_default_data(struct plat_stmmacenet_data *plat)$/;"	f	typeref:typename:void	file:
common_default_data	stmmac_pci.c	/^static void common_default_data(struct plat_stmmacenet_data *plat)$/;"	f	typeref:typename:void	file:
comp	stmmac_selftests.c	/^	struct completion comp;$/;"	m	struct:stmmac_test_priv	typeref:struct:completion	file:
config_addend	hwif.h	/^	int (*config_addend) (void __iomem *ioaddr, u32 addend);$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:int (*)(void __iomem * ioaddr,u32 addend)
config_addend	stmmac_hwtstamp.c	/^static int config_addend(void __iomem *ioaddr, u32 addend)$/;"	f	typeref:typename:int	file:
config_cbs	hwif.h	/^	void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 send_slope,u32 idle_slope,u32 high_credit,u32 low_credit,u32 queue)
config_hw_tstamping	hwif.h	/^	void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:void (*)(void __iomem * ioaddr,u32 data)
config_hw_tstamping	stmmac_hwtstamp.c	/^static void config_hw_tstamping(void __iomem *ioaddr, u32 data)$/;"	f	typeref:typename:void	file:
config_l3_filter	hwif.h	/^	int (*config_l3_filter)(struct mac_device_info *hw, u32 filter_no,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,u32 filter_no,bool en,bool ipv6,bool sa,bool inv,u32 match)
config_l4_filter	hwif.h	/^	int (*config_l4_filter)(struct mac_device_info *hw, u32 filter_no,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,u32 filter_no,bool en,bool udp,bool sa,bool inv,u32 match)
config_sub_second_increment	hwif.h	/^	void (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:void (*)(void __iomem * ioaddr,u32 ptp_clock,int gmac4,u32 * ssinc)
config_sub_second_increment	stmmac_hwtstamp.c	/^static void config_sub_second_increment(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
cookie	stmmac.h	/^	unsigned long cookie;$/;"	m	struct:stmmac_flow_entry	typeref:typename:unsigned long
core_clk	dwmac-ipq806x.c	/^	struct clk *core_clk;$/;"	m	struct:ipq806x_gmac	typeref:struct:clk *	file:
core_init	hwif.h	/^	void (*core_init)(struct mac_device_info *hw, struct net_device *dev);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,struct net_device * dev)
csum_none	common.h	/^	csum_none = 0x2,$/;"	e	enum:rx_frame_status
ctl_block	dwmac-anarion.c	/^	uintptr_t ctl_block;$/;"	m	struct:anarion_gmac	typeref:typename:uintptr_t	file:
ctrl	hwif.h	/^	void (*ctrl)(void __iomem *ioaddr, unsigned int mode);$/;"	m	struct:stmmac_mmc_ops	typeref:typename:void (*)(void __iomem * ioaddr,unsigned int mode)
ctrl_reg	dwmac-sti.c	/^	u32 ctrl_reg;		\/* GMAC glue-logic control register *\/$/;"	m	struct:sti_dwmac	typeref:typename:u32	file:
cur_rx	stmmac.h	/^	unsigned int cur_rx;$/;"	m	struct:stmmac_rx_queue	typeref:typename:unsigned int
cur_tx	stmmac.h	/^	unsigned int cur_tx;$/;"	m	struct:stmmac_tx_queue	typeref:typename:unsigned int
da_rx_filter_fail	common.h	/^	unsigned long da_rx_filter_fail;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
data	common.h	/^	unsigned int data;	\/* MII Data *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
data	dwmac-intel-plat.c	/^	const struct intel_dwmac_data *data;$/;"	m	struct:intel_dwmac	typeref:typename:const struct intel_dwmac_data *	file:
data	dwmac-meson8b.c	/^	const struct meson8b_dwmac_data	*data;$/;"	m	struct:meson8b_dwmac	typeref:typename:const struct meson8b_dwmac_data *	file:
dbgfs_dir	stmmac.h	/^	struct dentry *dbgfs_dir;$/;"	m	struct:stmmac_priv	typeref:struct:dentry *
deac_full_minus_1	dwmac1000.h	/^	deac_full_minus_1 = 0x00400000,$/;"	e	enum:rfd
deac_full_minus_2	dwmac1000.h	/^	deac_full_minus_2 = 0x00400800,$/;"	e	enum:rfd
deac_full_minus_3	dwmac1000.h	/^	deac_full_minus_3 = 0x00401000,$/;"	e	enum:rfd
deac_full_minus_4	dwmac1000.h	/^	deac_full_minus_4 = 0x00401800,$/;"	e	enum:rfd
debug	hwif.h	/^	void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 rx_queues,u32 tx_queues)
debug	stmmac_main.c	/^static int debug = -1;$/;"	v	typeref:typename:int	file:
default_addend	stmmac.h	/^	unsigned int default_addend;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
default_msg_level	stmmac_main.c	/^static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |$/;"	v	typeref:typename:const u32	file:
default_syscon_value	dwmac-sun8i.c	/^	u32 default_syscon_value;$/;"	m	struct:emac_variant	typeref:typename:u32	file:
del_hw_vlan_rx_fltr	hwif.h	/^	int (*del_hw_vlan_rx_fltr)(struct net_device *dev,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct net_device * dev,struct mac_device_info * hw,__be16 proto,u16 vid)
des0	descs.h	/^	__le32 des0;$/;"	m	struct:dma_desc	typeref:typename:__le32
des1	descs.h	/^	__le32 des1;$/;"	m	struct:dma_desc	typeref:typename:__le32
des2	descs.h	/^	__le32 des2;$/;"	m	struct:dma_desc	typeref:typename:__le32
des3	descs.h	/^	__le32 des3;$/;"	m	struct:dma_desc	typeref:typename:__le32
des4	descs.h	/^	__le32 des4;	\/* Extended Status *\/$/;"	m	struct:dma_extended_desc	typeref:typename:__le32
des4	descs.h	/^	__le32 des4;$/;"	m	struct:dma_edesc	typeref:typename:__le32
des5	descs.h	/^	__le32 des5;	\/* Reserved *\/$/;"	m	struct:dma_extended_desc	typeref:typename:__le32
des5	descs.h	/^	__le32 des5;$/;"	m	struct:dma_edesc	typeref:typename:__le32
des6	descs.h	/^	__le32 des6;	\/* Tx\/Rx Timestamp Low *\/$/;"	m	struct:dma_extended_desc	typeref:typename:__le32
des6	descs.h	/^	__le32 des6;$/;"	m	struct:dma_edesc	typeref:typename:__le32
des7	descs.h	/^	__le32 des7;	\/* Tx\/Rx Timestamp High *\/$/;"	m	struct:dma_extended_desc	typeref:typename:__le32
des7	descs.h	/^	__le32 des7;$/;"	m	struct:dma_edesc	typeref:typename:__le32
desc	common.h	/^	const struct stmmac_desc_ops *desc;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_desc_ops *
desc	dwmac5.c	/^	const char *desc;$/;"	m	struct:dwmac5_error_desc	typeref:typename:const char *	file:
desc	dwmac5.c	/^	const struct dwmac5_error_desc *desc;$/;"	m	struct:dwmac5_error	typeref:typename:const struct dwmac5_error_desc *	file:
desc	dwxgmac2_core.c	/^	const char *desc;$/;"	m	struct:dwxgmac3_error_desc	typeref:typename:const char *	file:
desc	dwxgmac2_core.c	/^	const struct dwxgmac3_error_desc *desc;$/;"	m	struct:dwxgmac3_error	typeref:typename:const struct dwxgmac3_error_desc *	file:
desc	hwif.c	/^	const void *desc;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
detailed_desc	dwmac5.c	/^	const char *detailed_desc;$/;"	m	struct:dwmac5_error_desc	typeref:typename:const char *	file:
detailed_desc	dwxgmac2_core.c	/^	const char *detailed_desc;$/;"	m	struct:dwxgmac3_error_desc	typeref:typename:const char *	file:
dev	altr_tse_pcs.h	/^	struct device *dev;$/;"	m	struct:tse_pcs	typeref:struct:device *
dev	dwmac-dwc-qos-eth.c	/^	struct device *dev;$/;"	m	struct:tegra_eqos	typeref:struct:device *	file:
dev	dwmac-imx.c	/^	struct device *dev;$/;"	m	struct:imx_priv_data	typeref:struct:device *	file:
dev	dwmac-intel-plat.c	/^	struct device *dev;$/;"	m	struct:intel_dwmac	typeref:struct:device *	file:
dev	dwmac-mediatek.c	/^	struct device *dev;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:struct:device *	file:
dev	dwmac-meson.c	/^	struct device	*dev;$/;"	m	struct:meson_dwmac	typeref:struct:device *	file:
dev	dwmac-meson8b.c	/^	struct device			*dev;$/;"	m	struct:meson8b_dwmac	typeref:struct:device *	file:
dev	dwmac-oxnas.c	/^	struct device	*dev;$/;"	m	struct:oxnas_dwmac	typeref:struct:device *	file:
dev	dwmac-socfpga.c	/^	struct	device *dev;$/;"	m	struct:socfpga_dwmac	typeref:struct:device *	file:
dev	dwmac-stm32.c	/^	struct device *dev;$/;"	m	struct:stm32_dwmac	typeref:struct:device *	file:
dev	stmmac.h	/^	struct net_device *dev;$/;"	m	struct:stmmac_priv	typeref:struct:net_device *
dev_id	hwif.c	/^	u32 dev_id;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:u32	file:
device	stmmac.h	/^	struct device *device;$/;"	m	struct:stmmac_priv	typeref:struct:device *
dirty_rx	stmmac.h	/^	unsigned int dirty_rx;$/;"	m	struct:stmmac_rx_queue	typeref:typename:unsigned int
dirty_tx	stmmac.h	/^	unsigned int dirty_tx;$/;"	m	struct:stmmac_tx_queue	typeref:typename:unsigned int
disable_dma_irq	hwif.h	/^	void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan,bool rx,bool tx)
discard_frame	common.h	/^	discard_frame = 0x1,$/;"	e	enum:rx_frame_status
display_ring	hwif.h	/^	void (*display_ring)(void *head, unsigned int size, bool rx,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(void * head,unsigned int size,bool rx,dma_addr_t dma_rx_phy,unsigned int desc_size)
dma	common.h	/^	const struct stmmac_dma_ops *dma;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_dma_ops *
dma	hwif.c	/^	const void *dma;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
dma_bit_mask	dwmac-mediatek.c	/^	u32 dma_bit_mask;$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:u32	file:
dma_buf_sz	stmmac.h	/^	unsigned int dma_buf_sz;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
dma_cap	stmmac.h	/^	struct dma_features dma_cap;$/;"	m	struct:stmmac_priv	typeref:struct:dma_features
dma_ch_no	stmmac.h	/^		u8 dma_ch_no;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8
dma_desc	descs.h	/^struct dma_desc {$/;"	s
dma_diagnostic_fr	hwif.h	/^	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void * data,struct stmmac_extra_stats * x,void __iomem * ioaddr)
dma_edesc	descs.h	/^struct dma_edesc {$/;"	s
dma_entx	stmmac.h	/^	struct dma_edesc *dma_entx;$/;"	m	struct:stmmac_tx_queue	typeref:struct:dma_edesc *
dma_errors	common.h	/^	unsigned long dma_errors[32];$/;"	m	struct:stmmac_safety_stats	typeref:typename:unsigned long[32]
dma_erx	stmmac.h	/^	struct dma_extended_desc *dma_erx;$/;"	m	struct:stmmac_rx_queue	typeref:struct:dma_extended_desc *
dma_extended_desc	descs.h	/^struct dma_extended_desc {$/;"	s
dma_features	common.h	/^struct dma_features {$/;"	s
dma_free_rx_skbufs	stmmac_main.c	/^static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
dma_free_tx_skbufs	stmmac_main.c	/^static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
dma_interrupt	hwif.h	/^	int (*dma_interrupt) (void __iomem *ioaddr,$/;"	m	struct:stmmac_dma_ops	typeref:typename:int (*)(void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan)
dma_irq_status	common.h	/^enum dma_irq_status {$/;"	g
dma_own	common.h	/^	dma_own = 0x8,$/;"	e	enum:rx_frame_status
dma_rx_mode	hwif.h	/^	void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)
dma_rx_phy	stmmac.h	/^	dma_addr_t dma_rx_phy;$/;"	m	struct:stmmac_rx_queue	typeref:typename:dma_addr_t
dma_rx_size	stmmac.h	/^	unsigned int dma_rx_size;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
dma_tx	stmmac.h	/^	struct dma_desc *dma_tx;$/;"	m	struct:stmmac_tx_queue	typeref:struct:dma_desc *
dma_tx_mode	hwif.h	/^	void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)
dma_tx_phy	stmmac.h	/^	dma_addr_t dma_tx_phy;$/;"	m	struct:stmmac_tx_queue	typeref:typename:dma_addr_t
dma_tx_size	stmmac.h	/^	unsigned int dma_tx_size;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
dont_wait	stmmac_selftests.c	/^	int dont_wait;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
double_ratio	dwmac1000.h	/^	double_ratio = 0x00004000,	\/* 2:1 *\/$/;"	e	enum:rx_tx_priority_ratio
double_vlan	stmmac_selftests.c	/^	int double_vlan;$/;"	m	struct:stmmac_test_priv	typeref:typename:int	file:
dport	stmmac_selftests.c	/^	int dport;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
dribbling_bit	common.h	/^	unsigned long dribbling_bit;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
dst	stmmac_selftests.c	/^	unsigned char *dst;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:unsigned char *	file:
dump_regs	hwif.h	/^	void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 * reg_space)
dump_regs	hwif.h	/^	void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 * reg_space)
duplex	common.h	/^	u32 duplex;$/;"	m	struct:mac_link	typeref:typename:u32
duplex	common.h	/^	unsigned int duplex;$/;"	m	struct:rgmii_adv	typeref:typename:unsigned int
dvlan	common.h	/^	unsigned int dvlan;$/;"	m	struct:dma_features	typeref:typename:unsigned int
dwc_eth_dwmac_config_dt	dwmac-dwc-qos-eth.c	/^static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,$/;"	f	typeref:typename:int	file:
dwc_eth_dwmac_data	dwmac-dwc-qos-eth.c	/^struct dwc_eth_dwmac_data {$/;"	s	file:
dwc_eth_dwmac_driver	dwmac-dwc-qos-eth.c	/^static struct platform_driver dwc_eth_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
dwc_eth_dwmac_match	dwmac-dwc-qos-eth.c	/^static const struct of_device_id dwc_eth_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
dwc_eth_dwmac_probe	dwmac-dwc-qos-eth.c	/^static int dwc_eth_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
dwc_eth_dwmac_remove	dwmac-dwc-qos-eth.c	/^static int dwc_eth_dwmac_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
dwc_qos_data	dwmac-dwc-qos-eth.c	/^static const struct dwc_eth_dwmac_data dwc_qos_data = {$/;"	v	typeref:typename:const struct dwc_eth_dwmac_data	file:
dwc_qos_probe	dwmac-dwc-qos-eth.c	/^static void *dwc_qos_probe(struct platform_device *pdev,$/;"	f	typeref:typename:void *	file:
dwc_qos_remove	dwmac-dwc-qos-eth.c	/^static int dwc_qos_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
dwmac-altr-socfpga-objs	Makefile	/^dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o$/;"	m
dwmac1000_configure_fc	dwmac1000_dma.c	/^static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)$/;"	f	typeref:typename:u32	file:
dwmac1000_core_init	dwmac1000_core.c	/^static void dwmac1000_core_init(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac1000_ctrl_ane	dwmac1000_core.c	/^static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,$/;"	f	typeref:typename:void	file:
dwmac1000_debug	dwmac1000_core.c	/^static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_axi	dwmac1000_dma.c	/^static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)$/;"	f	typeref:typename:void	file:
dwmac1000_dma_init	dwmac1000_dma.c	/^static void dwmac1000_dma_init(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_init_rx	dwmac1000_dma.c	/^static void dwmac1000_dma_init_rx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_init_tx	dwmac1000_dma.c	/^static void dwmac1000_dma_init_tx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_operation_mode_rx	dwmac1000_dma.c	/^static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_operation_mode_tx	dwmac1000_dma.c	/^static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwmac1000_dma_ops	dwmac1000_dma.c	/^const struct stmmac_dma_ops dwmac1000_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops
dwmac1000_dump_dma_regs	dwmac1000_dma.c	/^static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac1000_dump_regs	dwmac1000_core.c	/^static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac1000_flow_ctrl	dwmac1000_core.c	/^static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,$/;"	f	typeref:typename:void	file:
dwmac1000_get_adv_lp	dwmac1000_core.c	/^static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)$/;"	f	typeref:typename:void	file:
dwmac1000_get_hw_feature	dwmac1000_dma.c	/^static int dwmac1000_get_hw_feature(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwmac1000_get_umac_addr	dwmac1000_core.c	/^static void dwmac1000_get_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac1000_irq_status	dwmac1000_core.c	/^static int dwmac1000_irq_status(struct mac_device_info *hw,$/;"	f	typeref:typename:int	file:
dwmac1000_ops	dwmac1000_core.c	/^const struct stmmac_ops dwmac1000_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwmac1000_pmt	dwmac1000_core.c	/^static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)$/;"	f	typeref:typename:void	file:
dwmac1000_rane	dwmac1000_core.c	/^static void dwmac1000_rane(void __iomem *ioaddr, bool restart)$/;"	f	typeref:typename:void	file:
dwmac1000_reset_eee_mode	dwmac1000_core.c	/^static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)$/;"	f	typeref:typename:void	file:
dwmac1000_rgsmii	dwmac1000_core.c	/^static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)$/;"	f	typeref:typename:void	file:
dwmac1000_rx_ipc_enable	dwmac1000_core.c	/^static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
dwmac1000_rx_watchdog	dwmac1000_dma.c	/^static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,$/;"	f	typeref:typename:void	file:
dwmac1000_set_eee_mode	dwmac1000_core.c	/^static void dwmac1000_set_eee_mode(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac1000_set_eee_pls	dwmac1000_core.c	/^static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)$/;"	f	typeref:typename:void	file:
dwmac1000_set_eee_timer	dwmac1000_core.c	/^static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)$/;"	f	typeref:typename:void	file:
dwmac1000_set_filter	dwmac1000_core.c	/^static void dwmac1000_set_filter(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac1000_set_mac_loopback	dwmac1000_core.c	/^static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
dwmac1000_set_mchash	dwmac1000_core.c	/^static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,$/;"	f	typeref:typename:void	file:
dwmac1000_set_umac_addr	dwmac1000_core.c	/^static void dwmac1000_set_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac1000_setup	dwmac1000_core.c	/^int dwmac1000_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
dwmac1000_validate_mcast_bins	stmmac_platform.c	/^static int dwmac1000_validate_mcast_bins(struct device *dev, int mcast_bins)$/;"	f	typeref:typename:int	file:
dwmac1000_validate_ucast_entries	stmmac_platform.c	/^static int dwmac1000_validate_ucast_entries(struct device *dev,$/;"	f	typeref:typename:int	file:
dwmac100_core_init	dwmac100_core.c	/^static void dwmac100_core_init(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac100_dma_diagnostic_fr	dwmac100_dma.c	/^static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:void	file:
dwmac100_dma_init	dwmac100_dma.c	/^static void dwmac100_dma_init(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac100_dma_init_rx	dwmac100_dma.c	/^static void dwmac100_dma_init_rx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac100_dma_init_tx	dwmac100_dma.c	/^static void dwmac100_dma_init_tx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac100_dma_operation_mode_tx	dwmac100_dma.c	/^static void dwmac100_dma_operation_mode_tx(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwmac100_dma_ops	dwmac100_dma.c	/^const struct stmmac_dma_ops dwmac100_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops
dwmac100_dump_dma_regs	dwmac100_dma.c	/^static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac100_dump_mac_regs	dwmac100_core.c	/^static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac100_flow_ctrl	dwmac100_core.c	/^static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,$/;"	f	typeref:typename:void	file:
dwmac100_get_umac_addr	dwmac100_core.c	/^static void dwmac100_get_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac100_irq_status	dwmac100_core.c	/^static int dwmac100_irq_status(struct mac_device_info *hw,$/;"	f	typeref:typename:int	file:
dwmac100_ops	dwmac100_core.c	/^const struct stmmac_ops dwmac100_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwmac100_pmt	dwmac100_core.c	/^static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)$/;"	f	typeref:typename:void	file:
dwmac100_rx_ipc_enable	dwmac100_core.c	/^static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
dwmac100_set_filter	dwmac100_core.c	/^static void dwmac100_set_filter(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac100_set_mac_loopback	dwmac100_core.c	/^static void dwmac100_set_mac_loopback(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
dwmac100_set_umac_addr	dwmac100_core.c	/^static void dwmac100_set_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac100_setup	dwmac100_core.c	/^int dwmac100_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
dwmac410_disable_dma_irq	dwmac4_lib.c	/^void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac410_dma_init_channel	dwmac4_dma.c	/^static void dwmac410_dma_init_channel(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac410_dma_ops	dwmac4_dma.c	/^const struct stmmac_dma_ops dwmac410_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops
dwmac410_enable_dma_irq	dwmac4_lib.c	/^void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac410_ops	dwmac4_core.c	/^const struct stmmac_ops dwmac410_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwmac4_add_hw_vlan_rx_fltr	dwmac4_core.c	/^static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,$/;"	f	typeref:typename:int	file:
dwmac4_clear	dwmac4_descs.c	/^static void dwmac4_clear(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwmac4_config_cbs	dwmac4_core.c	/^static void dwmac4_config_cbs(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_config_l3_filter	dwmac4_core.c	/^static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwmac4_config_l4_filter	dwmac4_core.c	/^static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwmac4_core_init	dwmac4_core.c	/^static void dwmac4_core_init(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_ctrl_ane	dwmac4_core.c	/^static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,$/;"	f	typeref:typename:void	file:
dwmac4_debug	dwmac4_core.c	/^static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:void	file:
dwmac4_del_hw_vlan_rx_fltr	dwmac4_core.c	/^static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,$/;"	f	typeref:typename:int	file:
dwmac4_desc_ops	dwmac4_descs.c	/^const struct stmmac_desc_ops dwmac4_desc_ops = {$/;"	v	typeref:typename:const struct stmmac_desc_ops
dwmac4_disable_dma_irq	dwmac4_lib.c	/^void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac4_display_ring	dwmac4_descs.c	/^static void dwmac4_display_ring(void *head, unsigned int size, bool rx,$/;"	f	typeref:typename:void	file:
dwmac4_dma_axi	dwmac4_dma.c	/^static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)$/;"	f	typeref:typename:void	file:
dwmac4_dma_init	dwmac4_dma.c	/^static void dwmac4_dma_init(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac4_dma_init_channel	dwmac4_dma.c	/^static void dwmac4_dma_init_channel(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac4_dma_init_rx_chan	dwmac4_dma.c	/^static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac4_dma_init_tx_chan	dwmac4_dma.c	/^static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwmac4_dma_interrupt	dwmac4_lib.c	/^int dwmac4_dma_interrupt(void __iomem *ioaddr,$/;"	f	typeref:typename:int
dwmac4_dma_ops	dwmac4_dma.c	/^const struct stmmac_dma_ops dwmac4_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops
dwmac4_dma_reset	dwmac4_lib.c	/^int dwmac4_dma_reset(void __iomem *ioaddr)$/;"	f	typeref:typename:int
dwmac4_dma_rx_chan_op_mode	dwmac4_dma.c	/^static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwmac4_dma_start_rx	dwmac4_lib.c	/^void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_dma_start_tx	dwmac4_lib.c	/^void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_dma_stop_rx	dwmac4_lib.c	/^void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_dma_stop_tx	dwmac4_lib.c	/^void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_dma_tx_chan_op_mode	dwmac4_dma.c	/^static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwmac4_dump_dma_regs	dwmac4_dma.c	/^static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac4_dump_regs	dwmac4_core.c	/^static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwmac4_enable_dma_irq	dwmac4_lib.c	/^void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac4_enable_sph	dwmac4_dma.c	/^static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:void	file:
dwmac4_enable_tbs	dwmac4_dma.c	/^static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:int	file:
dwmac4_enable_tso	dwmac4_dma.c	/^static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:void	file:
dwmac4_enable_vlan	dwmac4_core.c	/^static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)$/;"	f	typeref:typename:void	file:
dwmac4_flow_ctrl	dwmac4_core.c	/^static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,$/;"	f	typeref:typename:void	file:
dwmac4_get_addr	dwmac4_descs.c	/^static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)$/;"	f	typeref:typename:void	file:
dwmac4_get_adv_lp	dwmac4_core.c	/^static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)$/;"	f	typeref:typename:void	file:
dwmac4_get_hw_feature	dwmac4_dma.c	/^static int dwmac4_get_hw_feature(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwmac4_get_num_vlan	dwmac4_core.c	/^static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)$/;"	f	typeref:typename:u32	file:
dwmac4_get_rx_header_len	dwmac4_descs.c	/^static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)$/;"	f	typeref:typename:void	file:
dwmac4_get_timestamp	dwmac4_descs.c	/^static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)$/;"	f	typeref:typename:void	file:
dwmac4_get_tx_ls	dwmac4_descs.c	/^static int dwmac4_get_tx_ls(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwmac4_get_tx_owner	dwmac4_descs.c	/^static int dwmac4_get_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwmac4_get_umac_addr	dwmac4_core.c	/^static void dwmac4_get_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_irq_mtl_status	dwmac4_core.c	/^static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)$/;"	f	typeref:typename:int	file:
dwmac4_irq_status	dwmac4.h	/^enum dwmac4_irq_status {$/;"	g
dwmac4_irq_status	dwmac4_core.c	/^static int dwmac4_irq_status(struct mac_device_info *hw,$/;"	f	typeref:typename:int	file:
dwmac4_map_mtl_dma	dwmac4_core.c	/^static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)$/;"	f	typeref:typename:void	file:
dwmac4_ops	dwmac4_core.c	/^const struct stmmac_ops dwmac4_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwmac4_phystatus	dwmac4_core.c	/^static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)$/;"	f	typeref:typename:void	file:
dwmac4_pmt	dwmac4_core.c	/^static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)$/;"	f	typeref:typename:void	file:
dwmac4_prog_mtl_rx_algorithms	dwmac4_core.c	/^static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_prog_mtl_tx_algorithms	dwmac4_core.c	/^static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_qmode	dwmac4_dma.c	/^static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)$/;"	f	typeref:typename:void	file:
dwmac4_rane	dwmac4_core.c	/^static void dwmac4_rane(void __iomem *ioaddr, bool restart)$/;"	f	typeref:typename:void	file:
dwmac4_rd_enable_tx_timestamp	dwmac4_descs.c	/^static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwmac4_rd_get_tx_len	dwmac4_descs.c	/^static int dwmac4_rd_get_tx_len(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwmac4_rd_init_rx_desc	dwmac4_descs.c	/^static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,$/;"	f	typeref:typename:void	file:
dwmac4_rd_init_tx_desc	dwmac4_descs.c	/^static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)$/;"	f	typeref:typename:void	file:
dwmac4_rd_prepare_tso_tx_desc	dwmac4_descs.c	/^static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,$/;"	f	typeref:typename:void	file:
dwmac4_rd_prepare_tx_desc	dwmac4_descs.c	/^static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,$/;"	f	typeref:typename:void	file:
dwmac4_rd_set_tx_ic	dwmac4_descs.c	/^static void dwmac4_rd_set_tx_ic(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwmac4_release_tx_desc	dwmac4_descs.c	/^static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)$/;"	f	typeref:typename:void	file:
dwmac4_reset_eee_mode	dwmac4_core.c	/^static void dwmac4_reset_eee_mode(struct mac_device_info *hw)$/;"	f	typeref:typename:void	file:
dwmac4_restore_hw_vlan_rx_fltr	dwmac4_core.c	/^static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,$/;"	f	typeref:typename:void	file:
dwmac4_ring_mode_ops	dwmac4_descs.c	/^const struct stmmac_mode_ops dwmac4_ring_mode_ops = {$/;"	v	typeref:typename:const struct stmmac_mode_ops
dwmac4_rx_check_timestamp	dwmac4_descs.c	/^static int dwmac4_rx_check_timestamp(void *desc)$/;"	f	typeref:typename:int	file:
dwmac4_rx_ipc_enable	dwmac4_core.c	/^static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
dwmac4_rx_queue_enable	dwmac4_core.c	/^static void dwmac4_rx_queue_enable(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_rx_queue_priority	dwmac4_core.c	/^static void dwmac4_rx_queue_priority(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_rx_queue_routing	dwmac4_core.c	/^static void dwmac4_rx_queue_routing(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_rx_watchdog	dwmac4_dma.c	/^static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)$/;"	f	typeref:typename:void	file:
dwmac4_sarc_configure	dwmac4_core.c	/^static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)$/;"	f	typeref:typename:void	file:
dwmac4_set_addr	dwmac4_descs.c	/^static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)$/;"	f	typeref:typename:void	file:
dwmac4_set_arp_offload	dwmac4_core.c	/^static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,$/;"	f	typeref:typename:void	file:
dwmac4_set_bfsize	dwmac4_dma.c	/^static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)$/;"	f	typeref:typename:void	file:
dwmac4_set_eee_mode	dwmac4_core.c	/^static void dwmac4_set_eee_mode(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_set_eee_pls	dwmac4_core.c	/^static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)$/;"	f	typeref:typename:void	file:
dwmac4_set_eee_timer	dwmac4_core.c	/^static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)$/;"	f	typeref:typename:void	file:
dwmac4_set_filter	dwmac4_core.c	/^static void dwmac4_set_filter(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_set_mac_loopback	dwmac4_core.c	/^static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
dwmac4_set_mss_ctxt	dwmac4_descs.c	/^static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)$/;"	f	typeref:typename:void	file:
dwmac4_set_mtl_tx_queue_weight	dwmac4_core.c	/^static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_set_rx_owner	dwmac4_descs.c	/^static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)$/;"	f	typeref:typename:void	file:
dwmac4_set_rx_ring_len	dwmac4_lib.c	/^void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)$/;"	f	typeref:typename:void
dwmac4_set_rx_tail_ptr	dwmac4_lib.c	/^void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_set_sarc	dwmac4_descs.c	/^static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)$/;"	f	typeref:typename:void	file:
dwmac4_set_sec_addr	dwmac4_descs.c	/^static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)$/;"	f	typeref:typename:void	file:
dwmac4_set_tbs	dwmac4_descs.c	/^static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)$/;"	f	typeref:typename:void	file:
dwmac4_set_tx_owner	dwmac4_descs.c	/^static void dwmac4_set_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwmac4_set_tx_ring_len	dwmac4_lib.c	/^void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)$/;"	f	typeref:typename:void
dwmac4_set_tx_tail_ptr	dwmac4_lib.c	/^void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)$/;"	f	typeref:typename:void
dwmac4_set_umac_addr	dwmac4_core.c	/^static void dwmac4_set_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_set_vlan	dwmac4_descs.c	/^static void dwmac4_set_vlan(struct dma_desc *p, u32 type)$/;"	f	typeref:typename:void	file:
dwmac4_set_vlan_tag	dwmac4_descs.c	/^static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,$/;"	f	typeref:typename:void	file:
dwmac4_setup	dwmac4_core.c	/^int dwmac4_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
dwmac4_tx_queue_priority	dwmac4_core.c	/^static void dwmac4_tx_queue_priority(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwmac4_update_vlan_hash	dwmac4_core.c	/^static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,$/;"	f	typeref:typename:void	file:
dwmac4_vlan_promisc_enable	dwmac4_core.c	/^static void dwmac4_vlan_promisc_enable(struct net_device *dev,$/;"	f	typeref:typename:void	file:
dwmac4_wrback_get_rx_frame_len	dwmac4_descs.c	/^static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)$/;"	f	typeref:typename:int	file:
dwmac4_wrback_get_rx_status	dwmac4_descs.c	/^static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
dwmac4_wrback_get_rx_timestamp_status	dwmac4_descs.c	/^static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,$/;"	f	typeref:typename:int	file:
dwmac4_wrback_get_tx_status	dwmac4_descs.c	/^static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
dwmac4_wrback_get_tx_timestamp_status	dwmac4_descs.c	/^static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwmac4_write_single_vlan	dwmac4_core.c	/^static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)$/;"	f	typeref:typename:void	file:
dwmac4_write_vlan_filter	dwmac4_core.c	/^static int dwmac4_write_vlan_filter(struct net_device *dev,$/;"	f	typeref:typename:int	file:
dwmac510_ops	dwmac4_core.c	/^const struct stmmac_ops dwmac510_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwmac510_tc_ops	stmmac_tc.c	/^const struct stmmac_tc_ops dwmac510_tc_ops = {$/;"	v	typeref:typename:const struct stmmac_tc_ops
dwmac5_all_errors	dwmac5.c	/^} dwmac5_all_errors[] = {$/;"	v	typeref:typename:const struct dwmac5_error[]
dwmac5_dma_errors	dwmac5.c	/^static const struct dwmac5_error_desc dwmac5_dma_errors[32]= {$/;"	v	typeref:typename:const struct dwmac5_error_desc[32]	file:
dwmac5_error	dwmac5.c	/^static const struct dwmac5_error {$/;"	s	file:
dwmac5_error_desc	dwmac5.c	/^struct dwmac5_error_desc {$/;"	s	file:
dwmac5_est_configure	dwmac5.c	/^int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,$/;"	f	typeref:typename:int
dwmac5_est_write	dwmac5.c	/^static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)$/;"	f	typeref:typename:int	file:
dwmac5_flex_pps_config	dwmac5.c	/^int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,$/;"	f	typeref:typename:int
dwmac5_fpe_configure	dwmac5.c	/^void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,$/;"	f	typeref:typename:void
dwmac5_handle_dma_err	dwmac5.c	/^static void dwmac5_handle_dma_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwmac5_handle_mac_err	dwmac5.c	/^static void dwmac5_handle_mac_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwmac5_handle_mtl_err	dwmac5.c	/^static void dwmac5_handle_mtl_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwmac5_log_error	dwmac5.c	/^static void dwmac5_log_error(struct net_device *ndev, u32 value, bool corr,$/;"	f	typeref:typename:void	file:
dwmac5_mac_errors	dwmac5.c	/^static const struct dwmac5_error_desc dwmac5_mac_errors[32]= {$/;"	v	typeref:typename:const struct dwmac5_error_desc[32]	file:
dwmac5_mtl_errors	dwmac5.c	/^static const struct dwmac5_error_desc dwmac5_mtl_errors[32]= {$/;"	v	typeref:typename:const struct dwmac5_error_desc[32]	file:
dwmac5_rxp_config	dwmac5.c	/^int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,$/;"	f	typeref:typename:int
dwmac5_rxp_disable	dwmac5.c	/^static int dwmac5_rxp_disable(void __iomem *ioaddr)$/;"	f	typeref:typename:int	file:
dwmac5_rxp_enable	dwmac5.c	/^static void dwmac5_rxp_enable(void __iomem *ioaddr)$/;"	f	typeref:typename:void	file:
dwmac5_rxp_get_next_entry	dwmac5.c	/^dwmac5_rxp_get_next_entry(struct stmmac_tc_entry *entries, unsigned int count,$/;"	f	typeref:struct:stmmac_tc_entry *	file:
dwmac5_rxp_update_single_entry	dwmac5.c	/^static int dwmac5_rxp_update_single_entry(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwmac5_safety_feat_config	dwmac5.c	/^int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)$/;"	f	typeref:typename:int
dwmac5_safety_feat_dump	dwmac5.c	/^int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,$/;"	f	typeref:typename:int
dwmac5_safety_feat_irq_status	dwmac5.c	/^int dwmac5_safety_feat_irq_status(struct net_device *ndev,$/;"	f	typeref:typename:int
dwmac_acpi_ids	dwmac-generic.c	/^#define dwmac_acpi_ids /;"	d	file:
dwmac_acpi_ids	dwmac-generic.c	/^static const struct acpi_device_id dwmac_acpi_ids[] = {$/;"	v	typeref:typename:const struct acpi_device_id[]	file:
dwmac_ctrl_ane	stmmac_pcs.h	/^static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,$/;"	f	typeref:typename:void
dwmac_disable_dma_irq	dwmac_lib.c	/^void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac_dma_flush_tx_fifo	dwmac_lib.c	/^void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)$/;"	f	typeref:typename:void
dwmac_dma_interrupt	dwmac_lib.c	/^int dwmac_dma_interrupt(void __iomem *ioaddr,$/;"	f	typeref:typename:int
dwmac_dma_reset	dwmac_lib.c	/^int dwmac_dma_reset(void __iomem *ioaddr)$/;"	f	typeref:typename:int
dwmac_dma_start_rx	dwmac_lib.c	/^void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac_dma_start_tx	dwmac_lib.c	/^void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac_dma_stop_rx	dwmac_lib.c	/^void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac_dma_stop_tx	dwmac_lib.c	/^void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void
dwmac_enable_dma_irq	dwmac_lib.c	/^void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)$/;"	f	typeref:typename:void
dwmac_enable_dma_transmission	dwmac_lib.c	/^void dwmac_enable_dma_transmission(void __iomem *ioaddr)$/;"	f	typeref:typename:void
dwmac_generic_driver	dwmac-generic.c	/^static struct platform_driver dwmac_generic_driver = {$/;"	v	typeref:struct:platform_driver	file:
dwmac_generic_match	dwmac-generic.c	/^static const struct of_device_id dwmac_generic_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
dwmac_generic_probe	dwmac-generic.c	/^static int dwmac_generic_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
dwmac_get_adv_lp	stmmac_pcs.h	/^static inline void dwmac_get_adv_lp(void __iomem *ioaddr, u32 reg,$/;"	f	typeref:typename:void
dwmac_mmc_ctrl	mmc_core.c	/^static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)$/;"	f	typeref:typename:void	file:
dwmac_mmc_intr_all_mask	mmc_core.c	/^static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)$/;"	f	typeref:typename:void	file:
dwmac_mmc_ops	mmc_core.c	/^const struct stmmac_mmc_ops dwmac_mmc_ops = {$/;"	v	typeref:typename:const struct stmmac_mmc_ops
dwmac_mmc_read	mmc_core.c	/^static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)$/;"	f	typeref:typename:void	file:
dwmac_pcs_isr	stmmac_pcs.h	/^static inline void dwmac_pcs_isr(void __iomem *ioaddr, u32 reg,$/;"	f	typeref:typename:void
dwmac_rane	stmmac_pcs.h	/^static inline void dwmac_rane(void __iomem *ioaddr, u32 reg, bool restart)$/;"	f	typeref:typename:void
dwmac_set_delay	dwmac-mediatek.c	/^	int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:int (*)(struct mediatek_dwmac_plat_data * plat)	file:
dwmac_set_phy_interface	dwmac-mediatek.c	/^	int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:int (*)(struct mediatek_dwmac_plat_data * plat)	file:
dwxgmac210_desc_ops	dwxgmac2_descs.c	/^const struct stmmac_desc_ops dwxgmac210_desc_ops = {$/;"	v	typeref:typename:const struct stmmac_desc_ops
dwxgmac210_dma_ops	dwxgmac2_dma.c	/^const struct stmmac_dma_ops dwxgmac210_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops
dwxgmac210_ops	dwxgmac2_core.c	/^const struct stmmac_ops dwxgmac210_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwxgmac2_clear	dwxgmac2_descs.c	/^static void dwxgmac2_clear(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwxgmac2_config_cbs	dwxgmac2_core.c	/^static void dwxgmac2_config_cbs(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_config_l3_filter	dwxgmac2_core.c	/^static int dwxgmac2_config_l3_filter(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwxgmac2_config_l4_filter	dwxgmac2_core.c	/^static int dwxgmac2_config_l4_filter(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwxgmac2_core_init	dwxgmac2_core.c	/^static void dwxgmac2_core_init(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_disable_dma_irq	dwxgmac2_dma.c	/^static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_axi	dwxgmac2_dma.c	/^static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_dump_regs	dwxgmac2_dma.c	/^static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_init	dwxgmac2_dma.c	/^static void dwxgmac2_dma_init(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_init_chan	dwxgmac2_dma.c	/^static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_init_rx_chan	dwxgmac2_dma.c	/^static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_init_tx_chan	dwxgmac2_dma.c	/^static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_interrupt	dwxgmac2_dma.c	/^static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwxgmac2_dma_reset	dwxgmac2_dma.c	/^static int dwxgmac2_dma_reset(void __iomem *ioaddr)$/;"	f	typeref:typename:int	file:
dwxgmac2_dma_rx_mode	dwxgmac2_dma.c	/^static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_start_rx	dwxgmac2_dma.c	/^static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_start_tx	dwxgmac2_dma.c	/^static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_stop_rx	dwxgmac2_dma.c	/^static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_stop_tx	dwxgmac2_dma.c	/^static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_dma_tx_mode	dwxgmac2_dma.c	/^static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
dwxgmac2_dump_regs	dwxgmac2_core.c	/^static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)$/;"	f	typeref:typename:void	file:
dwxgmac2_enable_dma_irq	dwxgmac2_dma.c	/^static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan,$/;"	f	typeref:typename:void	file:
dwxgmac2_enable_sph	dwxgmac2_dma.c	/^static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_enable_tbs	dwxgmac2_dma.c	/^static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:int	file:
dwxgmac2_enable_tso	dwxgmac2_dma.c	/^static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_enable_tx_timestamp	dwxgmac2_descs.c	/^static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwxgmac2_enable_vlan	dwxgmac2_core.c	/^static void dwxgmac2_enable_vlan(struct mac_device_info *hw, u32 type)$/;"	f	typeref:typename:void	file:
dwxgmac2_filter_read	dwxgmac2_core.c	/^static int dwxgmac2_filter_read(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwxgmac2_filter_wait	dwxgmac2_core.c	/^static int dwxgmac2_filter_wait(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
dwxgmac2_filter_write	dwxgmac2_core.c	/^static int dwxgmac2_filter_write(struct mac_device_info *hw, u32 filter_no,$/;"	f	typeref:typename:int	file:
dwxgmac2_flex_pps_config	dwxgmac2_core.c	/^static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,$/;"	f	typeref:typename:int	file:
dwxgmac2_flow_ctrl	dwxgmac2_core.c	/^static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,$/;"	f	typeref:typename:void	file:
dwxgmac2_get_addr	dwxgmac2_descs.c	/^static void dwxgmac2_get_addr(struct dma_desc *p, unsigned int *addr)$/;"	f	typeref:typename:void	file:
dwxgmac2_get_hw_feature	dwxgmac2_dma.c	/^static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwxgmac2_get_mac_tx_timestamp	dwxgmac2_core.c	/^static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_rx_frame_len	dwxgmac2_descs.c	/^static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_rx_hash	dwxgmac2_descs.c	/^static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,$/;"	f	typeref:typename:int	file:
dwxgmac2_get_rx_header_len	dwxgmac2_descs.c	/^static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)$/;"	f	typeref:typename:void	file:
dwxgmac2_get_rx_status	dwxgmac2_descs.c	/^static int dwxgmac2_get_rx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
dwxgmac2_get_rx_timestamp_status	dwxgmac2_descs.c	/^static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,$/;"	f	typeref:typename:int	file:
dwxgmac2_get_timestamp	dwxgmac2_descs.c	/^static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)$/;"	f	typeref:typename:void	file:
dwxgmac2_get_tx_len	dwxgmac2_descs.c	/^static int dwxgmac2_get_tx_len(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_tx_ls	dwxgmac2_descs.c	/^static int dwxgmac2_get_tx_ls(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_tx_owner	dwxgmac2_descs.c	/^static int dwxgmac2_get_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_tx_status	dwxgmac2_descs.c	/^static int dwxgmac2_get_tx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
dwxgmac2_get_tx_timestamp_status	dwxgmac2_descs.c	/^static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
dwxgmac2_get_umac_addr	dwxgmac2_core.c	/^static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_host_irq_status	dwxgmac2_core.c	/^static int dwxgmac2_host_irq_status(struct mac_device_info *hw,$/;"	f	typeref:typename:int	file:
dwxgmac2_host_mtl_irq_status	dwxgmac2_core.c	/^static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)$/;"	f	typeref:typename:int	file:
dwxgmac2_init_rx_desc	dwxgmac2_descs.c	/^static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,$/;"	f	typeref:typename:void	file:
dwxgmac2_init_tx_desc	dwxgmac2_descs.c	/^static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)$/;"	f	typeref:typename:void	file:
dwxgmac2_map_mtl_to_dma	dwxgmac2_core.c	/^static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,$/;"	f	typeref:typename:void	file:
dwxgmac2_pmt	dwxgmac2_core.c	/^static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)$/;"	f	typeref:typename:void	file:
dwxgmac2_prepare_tso_tx_desc	dwxgmac2_descs.c	/^static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,$/;"	f	typeref:typename:void	file:
dwxgmac2_prepare_tx_desc	dwxgmac2_descs.c	/^static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,$/;"	f	typeref:typename:void	file:
dwxgmac2_prog_mtl_rx_algorithms	dwxgmac2_core.c	/^static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_prog_mtl_tx_algorithms	dwxgmac2_core.c	/^static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_qmode	dwxgmac2_dma.c	/^static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)$/;"	f	typeref:typename:void	file:
dwxgmac2_release_tx_desc	dwxgmac2_descs.c	/^static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode)$/;"	f	typeref:typename:void	file:
dwxgmac2_reset_eee_mode	dwxgmac2_core.c	/^static void dwxgmac2_reset_eee_mode(struct mac_device_info *hw)$/;"	f	typeref:typename:void	file:
dwxgmac2_rss_configure	dwxgmac2_core.c	/^static int dwxgmac2_rss_configure(struct mac_device_info *hw,$/;"	f	typeref:typename:int	file:
dwxgmac2_rss_write_reg	dwxgmac2_core.c	/^static int dwxgmac2_rss_write_reg(void __iomem *ioaddr, bool is_key, int idx,$/;"	f	typeref:typename:int	file:
dwxgmac2_rx_check_timestamp	dwxgmac2_descs.c	/^static int dwxgmac2_rx_check_timestamp(void *desc)$/;"	f	typeref:typename:int	file:
dwxgmac2_rx_ipc	dwxgmac2_core.c	/^static int dwxgmac2_rx_ipc(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
dwxgmac2_rx_queue_enable	dwxgmac2_core.c	/^static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,$/;"	f	typeref:typename:void	file:
dwxgmac2_rx_queue_prio	dwxgmac2_core.c	/^static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,$/;"	f	typeref:typename:void	file:
dwxgmac2_rx_watchdog	dwxgmac2_dma.c	/^static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)$/;"	f	typeref:typename:void	file:
dwxgmac2_sarc_configure	dwxgmac2_core.c	/^static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_addr	dwxgmac2_descs.c	/^static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_arp_offload	dwxgmac2_core.c	/^static void dwxgmac2_set_arp_offload(struct mac_device_info *hw, bool en,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_bfsize	dwxgmac2_dma.c	/^static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_eee_mode	dwxgmac2_core.c	/^static void dwxgmac2_set_eee_mode(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_eee_pls	dwxgmac2_core.c	/^static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_eee_timer	dwxgmac2_core.c	/^static void dwxgmac2_set_eee_timer(struct mac_device_info *hw, int ls, int tw)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_filter	dwxgmac2_core.c	/^static void dwxgmac2_set_filter(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_mac	dwxgmac2_core.c	/^static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_mac_loopback	dwxgmac2_core.c	/^static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_mchash	dwxgmac2_core.c	/^static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_mss	dwxgmac2_descs.c	/^static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_mtl_tx_queue_weight	dwxgmac2_core.c	/^static void dwxgmac2_set_mtl_tx_queue_weight(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_rx_owner	dwxgmac2_descs.c	/^static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_rx_ring_len	dwxgmac2_dma.c	/^static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_rx_tail_ptr	dwxgmac2_dma.c	/^static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_sarc	dwxgmac2_descs.c	/^static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_sec_addr	dwxgmac2_descs.c	/^static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_tbs	dwxgmac2_descs.c	/^static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_tx_ic	dwxgmac2_descs.c	/^static void dwxgmac2_set_tx_ic(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_tx_owner	dwxgmac2_descs.c	/^static void dwxgmac2_set_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_tx_ring_len	dwxgmac2_dma.c	/^static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_tx_tail_ptr	dwxgmac2_dma.c	/^static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_umac_addr	dwxgmac2_core.c	/^static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
dwxgmac2_set_vlan	dwxgmac2_descs.c	/^static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)$/;"	f	typeref:typename:void	file:
dwxgmac2_set_vlan_tag	dwxgmac2_descs.c	/^static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,$/;"	f	typeref:typename:void	file:
dwxgmac2_setup	dwxgmac2_core.c	/^int dwxgmac2_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
dwxgmac2_tx_queue_prio	dwxgmac2_core.c	/^static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,$/;"	f	typeref:typename:void	file:
dwxgmac2_update_vlan_hash	dwxgmac2_core.c	/^static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,$/;"	f	typeref:typename:void	file:
dwxgmac3_all_errors	dwxgmac2_core.c	/^} dwxgmac3_all_errors[] = {$/;"	v	typeref:typename:const struct dwxgmac3_error[]
dwxgmac3_dma_errors	dwxgmac2_core.c	/^static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {$/;"	v	typeref:typename:const struct dwxgmac3_error_desc[32]	file:
dwxgmac3_error	dwxgmac2_core.c	/^static const struct dwxgmac3_error {$/;"	s	file:
dwxgmac3_error_desc	dwxgmac2_core.c	/^struct dwxgmac3_error_desc {$/;"	s	file:
dwxgmac3_est_configure	dwxgmac2_core.c	/^static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,$/;"	f	typeref:typename:int	file:
dwxgmac3_est_write	dwxgmac2_core.c	/^static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)$/;"	f	typeref:typename:int	file:
dwxgmac3_fpe_configure	dwxgmac2_core.c	/^static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 num_txq,$/;"	f	typeref:typename:void	file:
dwxgmac3_handle_dma_err	dwxgmac2_core.c	/^static void dwxgmac3_handle_dma_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwxgmac3_handle_mac_err	dwxgmac2_core.c	/^static void dwxgmac3_handle_mac_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwxgmac3_handle_mtl_err	dwxgmac2_core.c	/^static void dwxgmac3_handle_mtl_err(struct net_device *ndev,$/;"	f	typeref:typename:void	file:
dwxgmac3_log_error	dwxgmac2_core.c	/^static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,$/;"	f	typeref:typename:void	file:
dwxgmac3_mac_errors	dwxgmac2_core.c	/^static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {$/;"	v	typeref:typename:const struct dwxgmac3_error_desc[32]	file:
dwxgmac3_mtl_errors	dwxgmac2_core.c	/^static const struct dwxgmac3_error_desc dwxgmac3_mtl_errors[32]= {$/;"	v	typeref:typename:const struct dwxgmac3_error_desc[32]	file:
dwxgmac3_rxp_config	dwxgmac2_core.c	/^static int dwxgmac3_rxp_config(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwxgmac3_rxp_disable	dwxgmac2_core.c	/^static int dwxgmac3_rxp_disable(void __iomem *ioaddr)$/;"	f	typeref:typename:int	file:
dwxgmac3_rxp_enable	dwxgmac2_core.c	/^static void dwxgmac3_rxp_enable(void __iomem *ioaddr)$/;"	f	typeref:typename:void	file:
dwxgmac3_rxp_get_next_entry	dwxgmac2_core.c	/^dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry *entries,$/;"	f	typeref:struct:stmmac_tc_entry *	file:
dwxgmac3_rxp_update_single_entry	dwxgmac2_core.c	/^static int dwxgmac3_rxp_update_single_entry(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
dwxgmac3_safety_feat_config	dwxgmac2_core.c	/^static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp)$/;"	f	typeref:typename:int	file:
dwxgmac3_safety_feat_dump	dwxgmac2_core.c	/^static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,$/;"	f	typeref:typename:int	file:
dwxgmac3_safety_feat_irq_status	dwxgmac2_core.c	/^static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,$/;"	f	typeref:typename:int	file:
dwxgmac_mmc_ctrl	mmc_core.c	/^static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)$/;"	f	typeref:typename:void	file:
dwxgmac_mmc_intr_all_mask	mmc_core.c	/^static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)$/;"	f	typeref:typename:void	file:
dwxgmac_mmc_ops	mmc_core.c	/^const struct stmmac_mmc_ops dwxgmac_mmc_ops = {$/;"	v	typeref:typename:const struct stmmac_mmc_ops
dwxgmac_mmc_read	mmc_core.c	/^static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)$/;"	f	typeref:typename:void	file:
dwxgmac_read_mmc_reg	mmc_core.c	/^static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)$/;"	f	typeref:typename:void	file:
dwxlgmac2_ops	dwxgmac2_core.c	/^const struct stmmac_ops dwxlgmac2_ops = {$/;"	v	typeref:typename:const struct stmmac_ops
dwxlgmac2_rx_queue_enable	dwxgmac2_core.c	/^static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,$/;"	f	typeref:typename:void	file:
dwxlgmac2_setup	dwxgmac2_core.c	/^int dwxlgmac2_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
eee	common.h	/^	unsigned int eee;$/;"	m	struct:dma_features	typeref:typename:unsigned int
eee_active	stmmac.h	/^	int eee_active;$/;"	m	struct:stmmac_priv	typeref:typename:int
eee_ctrl_timer	stmmac.h	/^	struct timer_list eee_ctrl_timer;$/;"	m	struct:stmmac_priv	typeref:struct:timer_list
eee_enabled	stmmac.h	/^	int eee_enabled;$/;"	m	struct:stmmac_priv	typeref:typename:int
eee_timer	stmmac_main.c	/^static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;$/;"	v	typeref:typename:int	file:
eee_tw_timer	stmmac.h	/^	int eee_tw_timer;$/;"	m	struct:stmmac_priv	typeref:typename:int
ehl_common_data	dwmac-intel.c	/^static int ehl_common_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse0_common_data	dwmac-intel.c	/^static int ehl_pse0_common_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse0_rgmii1g_data	dwmac-intel.c	/^static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse0_rgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_pse0_sgmii1g_data	dwmac-intel.c	/^static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse0_sgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_pse1_common_data	dwmac-intel.c	/^static int ehl_pse1_common_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse1_rgmii1g_data	dwmac-intel.c	/^static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse1_rgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_pse1_sgmii1g_data	dwmac-intel.c	/^static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_pse1_sgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_rgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_rgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_rgmii_data	dwmac-intel.c	/^static int ehl_rgmii_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehl_sgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info ehl_sgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
ehl_sgmii_data	dwmac-intel.c	/^static int ehl_sgmii_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
ehn_desc_rx_set_on_chain	descs_com.h	/^static inline void ehn_desc_rx_set_on_chain(struct dma_desc *p)$/;"	f	typeref:typename:void
ehn_desc_rx_set_on_ring	descs_com.h	/^static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,$/;"	f	typeref:typename:void
emac_v2_3_0_data	dwmac-qcom-ethqos.c	/^static const struct ethqos_emac_driver_data emac_v2_3_0_data = {$/;"	v	typeref:typename:const struct ethqos_emac_driver_data	file:
emac_v2_3_0_por	dwmac-qcom-ethqos.c	/^static const struct ethqos_emac_por emac_v2_3_0_por[] = {$/;"	v	typeref:typename:const struct ethqos_emac_por[]	file:
emac_variant	dwmac-sun8i.c	/^struct emac_variant {$/;"	s	file:
emac_variant_a64	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_a64 = {$/;"	v	typeref:typename:const struct emac_variant	file:
emac_variant_a83t	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_a83t = {$/;"	v	typeref:typename:const struct emac_variant	file:
emac_variant_h3	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_h3 = {$/;"	v	typeref:typename:const struct emac_variant	file:
emac_variant_h6	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_h6 = {$/;"	v	typeref:typename:const struct emac_variant	file:
emac_variant_r40	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_r40 = {$/;"	v	typeref:typename:const struct emac_variant	file:
emac_variant_v3s	dwmac-sun8i.c	/^static const struct emac_variant emac_variant_v3s = {$/;"	v	typeref:typename:const struct emac_variant	file:
enable	stmmac.h	/^	int enable;$/;"	m	struct:stmmac_rss	typeref:typename:int
enable_dma_irq	hwif.h	/^	void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan,bool rx,bool tx)
enable_dma_transmission	hwif.h	/^	void (*enable_dma_transmission) (void __iomem *ioaddr);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr)
enable_eth_ck	dwmac-stm32.c	/^	int enable_eth_ck;$/;"	m	struct:stm32_dwmac	typeref:typename:int	file:
enable_sph	hwif.h	/^	void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool en,u32 chan)
enable_tbs	hwif.h	/^	int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:int (*)(void __iomem * ioaddr,bool en,u32 chan)
enable_tso	hwif.h	/^	void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool en,u32 chan)
enable_tx_timestamp	hwif.h	/^	void (*enable_tx_timestamp) (struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p)
enable_vlan	hwif.h	/^	void (*enable_vlan)(struct mac_device_info *hw, u32 type);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 type)
enh_desc	common.h	/^	unsigned int enh_desc;$/;"	m	struct:dma_features	typeref:typename:unsigned int
enh_desc_clear	enh_desc.c	/^static void enh_desc_clear(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
enh_desc_coe_rdes0	enh_desc.c	/^static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)$/;"	f	typeref:typename:int	file:
enh_desc_display_ring	enh_desc.c	/^static void enh_desc_display_ring(void *head, unsigned int size, bool rx,$/;"	f	typeref:typename:void	file:
enh_desc_enable_tx_timestamp	enh_desc.c	/^static void enh_desc_enable_tx_timestamp(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
enh_desc_end_tx_desc_on_chain	descs_com.h	/^static inline void enh_desc_end_tx_desc_on_chain(struct dma_desc *p)$/;"	f	typeref:typename:void
enh_desc_end_tx_desc_on_ring	descs_com.h	/^static inline void enh_desc_end_tx_desc_on_ring(struct dma_desc *p, int end)$/;"	f	typeref:typename:void
enh_desc_get_addr	enh_desc.c	/^static void enh_desc_get_addr(struct dma_desc *p, unsigned int *addr)$/;"	f	typeref:typename:void	file:
enh_desc_get_ext_status	enh_desc.c	/^static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:void	file:
enh_desc_get_rx_frame_len	enh_desc.c	/^static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)$/;"	f	typeref:typename:int	file:
enh_desc_get_rx_status	enh_desc.c	/^static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
enh_desc_get_rx_timestamp_status	enh_desc.c	/^static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc,$/;"	f	typeref:typename:int	file:
enh_desc_get_timestamp	enh_desc.c	/^static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts)$/;"	f	typeref:typename:void	file:
enh_desc_get_tx_len	enh_desc.c	/^static int enh_desc_get_tx_len(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
enh_desc_get_tx_ls	enh_desc.c	/^static int enh_desc_get_tx_ls(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
enh_desc_get_tx_owner	enh_desc.c	/^static int enh_desc_get_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
enh_desc_get_tx_status	enh_desc.c	/^static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
enh_desc_get_tx_timestamp_status	enh_desc.c	/^static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
enh_desc_init_rx_desc	enh_desc.c	/^static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,$/;"	f	typeref:typename:void	file:
enh_desc_init_tx_desc	enh_desc.c	/^static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)$/;"	f	typeref:typename:void	file:
enh_desc_ops	enh_desc.c	/^const struct stmmac_desc_ops enh_desc_ops = {$/;"	v	typeref:typename:const struct stmmac_desc_ops
enh_desc_prepare_tx_desc	enh_desc.c	/^static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,$/;"	f	typeref:typename:void	file:
enh_desc_release_tx_desc	enh_desc.c	/^static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)$/;"	f	typeref:typename:void	file:
enh_desc_set_addr	enh_desc.c	/^static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)$/;"	f	typeref:typename:void	file:
enh_desc_set_rx_owner	enh_desc.c	/^static void enh_desc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)$/;"	f	typeref:typename:void	file:
enh_desc_set_tx_ic	enh_desc.c	/^static void enh_desc_set_tx_ic(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
enh_desc_set_tx_owner	enh_desc.c	/^static void enh_desc_set_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
enh_set_tx_desc_len_on_chain	descs_com.h	/^static inline void enh_set_tx_desc_len_on_chain(struct dma_desc *p, int len)$/;"	f	typeref:typename:void
enh_set_tx_desc_len_on_ring	descs_com.h	/^static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)$/;"	f	typeref:typename:void
ephy_clk	dwmac-sun8i.c	/^	struct clk *ephy_clk;$/;"	m	struct:sunxi_priv_data	typeref:struct:clk *	file:
error	stmmac.h	/^		unsigned int error;$/;"	m	struct:stmmac_rx_queue::__anon84d70a400108	typeref:typename:unsigned int
est_configure	hwif.h	/^	int (*est_configure)(void __iomem *ioaddr, struct stmmac_est *cfg,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(void __iomem * ioaddr,struct stmmac_est * cfg,unsigned int ptp_rate)
estdep	common.h	/^	unsigned int estdep;$/;"	m	struct:dma_features	typeref:typename:unsigned int
estsel	common.h	/^	unsigned int estsel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
estwid	common.h	/^	unsigned int estwid;$/;"	m	struct:dma_features	typeref:typename:unsigned int
eth_clk_sel_reg	dwmac-stm32.c	/^	int eth_clk_sel_reg;$/;"	m	struct:stm32_dwmac	typeref:typename:int	file:
eth_ref_clk_sel_reg	dwmac-stm32.c	/^	int eth_ref_clk_sel_reg;$/;"	m	struct:stm32_dwmac	typeref:typename:int	file:
ethqos_configure	dwmac-qcom-ethqos.c	/^static int ethqos_configure(struct qcom_ethqos *ethqos)$/;"	f	typeref:typename:int	file:
ethqos_dll_configure	dwmac-qcom-ethqos.c	/^static int ethqos_dll_configure(struct qcom_ethqos *ethqos)$/;"	f	typeref:typename:int	file:
ethqos_emac_driver_data	dwmac-qcom-ethqos.c	/^struct ethqos_emac_driver_data {$/;"	s	file:
ethqos_emac_por	dwmac-qcom-ethqos.c	/^struct ethqos_emac_por {$/;"	s	file:
ethqos_fix_mac_speed	dwmac-qcom-ethqos.c	/^static void ethqos_fix_mac_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
ethqos_rgmii_macro_init	dwmac-qcom-ethqos.c	/^static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)$/;"	f	typeref:typename:int	file:
ethqos_set_func_clk_en	dwmac-qcom-ethqos.c	/^static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)$/;"	f	typeref:typename:void	file:
ethqos_update_rgmii_clk	dwmac-qcom-ethqos.c	/^ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)$/;"	f	typeref:typename:void	file:
exp_hash	stmmac_selftests.c	/^	u32 exp_hash;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u32	file:
ext_phyclk	dwmac-sti.c	/^	bool ext_phyclk;	\/* Clock from external PHY *\/$/;"	m	struct:sti_dwmac	typeref:typename:bool	file:
ext_phyclk	dwmac-stm32.c	/^	int ext_phyclk;$/;"	m	struct:stm32_dwmac	typeref:typename:int	file:
extend_desc	stmmac.h	/^	int extend_desc;$/;"	m	struct:stmmac_priv	typeref:typename:int
f2h_ptp_ref_clk	dwmac-socfpga.c	/^	bool f2h_ptp_ref_clk;$/;"	m	struct:socfpga_dwmac	typeref:typename:bool	file:
fatal_bus_error_irq	common.h	/^	unsigned long fatal_bus_error_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
fix_mac_speed	dwmac-intel-plat.c	/^	void (*fix_mac_speed)(void *priv, unsigned int speed);$/;"	m	struct:intel_dwmac_data	typeref:typename:void (*)(void * priv,unsigned int speed)	file:
fix_retime_src	dwmac-sti.c	/^	void (*fix_retime_src)(void *priv, unsigned int speed);$/;"	m	struct:sti_dwmac	typeref:typename:void (*)(void * priv,unsigned int speed)	file:
fix_retime_src	dwmac-sti.c	/^	void (*fix_retime_src)(void *priv, unsigned int speed);$/;"	m	struct:sti_dwmac_of_data	typeref:typename:void (*)(void * priv,unsigned int speed)	file:
fixed_div2	dwmac-meson8b.c	/^	struct clk_fixed_factor	fixed_div2;$/;"	m	struct:meson8b_dwmac_clk_configs	typeref:struct:clk_fixed_factor	file:
flex_pps_config	hwif.h	/^	int (*flex_pps_config)(void __iomem *ioaddr, int index,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(void __iomem * ioaddr,int index,struct stmmac_pps_cfg * cfg,bool enable,u32 sub_second_inc,u32 systime_flags)
flow_ctrl	hwif.h	/^	void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u32 tx_cnt)
flow_ctrl	stmmac.h	/^	unsigned int flow_ctrl;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
flow_ctrl	stmmac_main.c	/^static int flow_ctrl = FLOW_AUTO;$/;"	v	typeref:typename:int	file:
flow_entries	stmmac.h	/^	struct stmmac_flow_entry *flow_entries;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_flow_entry *
flow_entries_max	stmmac.h	/^	unsigned int flow_entries_max;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
fn	stmmac_selftests.c	/^	int (*fn)(struct stmmac_priv *priv);$/;"	m	struct:stmmac_test	typeref:typename:int (*)(struct stmmac_priv * priv)	file:
fn	stmmac_tc.c	/^	int (*fn)(struct stmmac_priv *priv, struct flow_cls_offload *cls,$/;"	m	struct:__anonf294d2f10108	typeref:typename:int (*)(struct stmmac_priv * priv,struct flow_cls_offload * cls,struct stmmac_flow_entry * entry)	file:
fpe_configure	hwif.h	/^	void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 num_txq,u32 num_rxq,bool enable)
fpesel	common.h	/^	unsigned int fpesel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
frag_ptr	stmmac.h	/^	void *frag_ptr;$/;"	m	struct:stmmac_tc_entry	typeref:typename:void *
frame_offset	stmmac.h	/^		u8 frame_offset;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8
free_dma_desc_resources	stmmac_main.c	/^static void free_dma_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
free_dma_rx_desc_resources	stmmac_main.c	/^static void free_dma_rx_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
free_dma_tx_desc_resources	stmmac_main.c	/^static void free_dma_tx_desc_resources(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
frpbs	common.h	/^	unsigned int frpbs;$/;"	m	struct:dma_features	typeref:typename:unsigned int
frpes	common.h	/^	unsigned int frpes;$/;"	m	struct:dma_features	typeref:typename:unsigned int
frpsel	common.h	/^	unsigned int frpsel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
func	dwmac-intel.c	/^	const struct stmmac_pci_func_data *func;$/;"	m	struct:stmmac_pci_dmi_data	typeref:typename:const struct stmmac_pci_func_data *	file:
func	dwmac-intel.c	/^	unsigned int func;$/;"	m	struct:stmmac_pci_func_data	typeref:typename:unsigned int	file:
fw_get_phy_mode	stmmac_platform.c	/^int fw_get_phy_mode(struct fwnode_handle *np)$/;"	f	typeref:typename:int
galileo_stmmac_dmi_data	dwmac-intel.c	/^static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {$/;"	v	typeref:typename:const struct stmmac_pci_dmi_data	file:
galileo_stmmac_func_data	dwmac-intel.c	/^static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {$/;"	v	typeref:typename:const struct stmmac_pci_func_data[]	file:
get_addr	hwif.h	/^	void (*get_addr)(struct dma_desc *p, unsigned int *addr);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,unsigned int * addr)
get_clk_div_rgmii	dwmac-ipq806x.c	/^static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)$/;"	f	typeref:typename:int	file:
get_clk_div_sgmii	dwmac-ipq806x.c	/^static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)$/;"	f	typeref:typename:int	file:
get_ephy_nodes	dwmac-sun8i.c	/^static int get_ephy_nodes(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
get_hw_feature	hwif.h	/^	int (*get_hw_feature)(void __iomem *ioaddr,$/;"	m	struct:stmmac_dma_ops	typeref:typename:int (*)(void __iomem * ioaddr,struct dma_features * dma_cap)
get_mac_tx_timestamp	hwif.h	/^	int (*get_mac_tx_timestamp)(struct mac_device_info *hw, u64 *ts);$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,u64 * ts)
get_rx_frame_len	hwif.h	/^	int (*get_rx_frame_len)(struct dma_desc *p, int rx_coe_type);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p,int rx_coe_type)
get_rx_hash	hwif.h	/^	int (*get_rx_hash)(struct dma_desc *p, u32 *hash,$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p,u32 * hash,enum pkt_hash_types * type)
get_rx_header_len	hwif.h	/^	void (*get_rx_header_len)(struct dma_desc *p, unsigned int *len);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,unsigned int * len)
get_rx_timestamp_status	hwif.h	/^	int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(void * desc,void * next_desc,u32 ats)
get_stmmac_bsp_priv	stmmac_platform.h	/^static inline void *get_stmmac_bsp_priv(struct device *dev)$/;"	f	typeref:typename:void *
get_systime	hwif.h	/^	void (*get_systime) (void __iomem *ioaddr, u64 *systime);$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:void (*)(void __iomem * ioaddr,u64 * systime)
get_systime	stmmac_hwtstamp.c	/^static void get_systime(void __iomem *ioaddr, u64 *systime)$/;"	f	typeref:typename:void	file:
get_timestamp	hwif.h	/^	void (*get_timestamp)(void *desc, u32 ats, u64 *ts);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(void * desc,u32 ats,u64 * ts)
get_tx_len	hwif.h	/^	int (*get_tx_len)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p)
get_tx_ls	hwif.h	/^	int (*get_tx_ls)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p)
get_tx_owner	hwif.h	/^	int (*get_tx_owner)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p)
get_tx_timestamp_status	hwif.h	/^	int (*get_tx_timestamp_status) (struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(struct dma_desc * p)
get_umac_addr	hwif.h	/^	void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)
global_unicast	dwmac1000.h	/^	global_unicast = 0x00000200,$/;"	e	enum:power_event
global_unicast	dwmac4.h	/^	global_unicast = 0x00000200,$/;"	e	enum:power_event
gmac	hwif.c	/^	bool gmac;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:bool	file:
gmac4	hwif.c	/^	bool gmac4;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:bool	file:
gmac_clk_enable	dwmac-rk.c	/^static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)$/;"	f	typeref:typename:int	file:
gmac_clkin	dwmac-rk.c	/^	struct clk *gmac_clkin;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
gmac_en	dwmac-sti.c	/^	bool gmac_en;$/;"	m	struct:sti_dwmac	typeref:typename:bool	file:
gmac_read_reg	dwmac-anarion.c	/^static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg)$/;"	f	typeref:typename:uint32_t	file:
gmac_write_reg	dwmac-anarion.c	/^static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val)$/;"	f	typeref:typename:void	file:
good_frame	common.h	/^	good_frame = 0x0,$/;"	e	enum:rx_frame_status
grf	dwmac-rk.c	/^	struct regmap *grf;$/;"	m	struct:rk_priv_data	typeref:struct:regmap *	file:
half_duplex	common.h	/^	unsigned int half_duplex;$/;"	m	struct:dma_features	typeref:typename:unsigned int
handle	stmmac.h	/^	u32 handle;$/;"	m	struct:stmmac_tc_entry	typeref:typename:u32
handle_rx	common.h	/^	handle_rx = 0x4,$/;"	e	enum:dma_irq_status
handle_tx	common.h	/^	handle_tx = 0x8,$/;"	e	enum:dma_irq_status
hash_filter	common.h	/^	unsigned int hash_filter;$/;"	m	struct:dma_features	typeref:typename:unsigned int
hash_tb_sz	common.h	/^	unsigned int hash_tb_sz;$/;"	m	struct:dma_features	typeref:typename:unsigned int
host_irq_status	hwif.h	/^	int (*host_irq_status)(struct mac_device_info *hw,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,struct stmmac_extra_stats * x)
host_mtl_irq_status	hwif.h	/^	int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,u32 chan)
hw	stmmac.h	/^	struct mac_device_info *hw;$/;"	m	struct:stmmac_priv	typeref:struct:mac_device_info *
hw_cap_support	stmmac.h	/^	int hw_cap_support;$/;"	m	struct:stmmac_priv	typeref:typename:int
hwif_quirks	stmmac.h	/^	int (*hwif_quirks)(struct stmmac_priv *priv);$/;"	m	struct:stmmac_priv	typeref:typename:int (*)(struct stmmac_priv * priv)
hwtimestamp	hwif.c	/^	const void *hwtimestamp;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
hwts_rx_en	stmmac.h	/^	int hwts_rx_en;$/;"	m	struct:stmmac_priv	typeref:typename:int
hwts_tx_en	stmmac.h	/^	int hwts_tx_en;$/;"	m	struct:stmmac_priv	typeref:typename:int
id	dwmac-ipq806x.c	/^	uint32_t id;$/;"	m	struct:ipq806x_gmac	typeref:typename:uint32_t	file:
id	stmmac_selftests.c	/^	u8 id;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u8	file:
id	stmmac_selftests.c	/^	u8 id;$/;"	m	struct:stmmachdr	typeref:typename:u8	file:
idx	stmmac.h	/^	int idx;$/;"	m	struct:stmmac_flow_entry	typeref:typename:int
im	stmmac.h	/^		u8 im:1;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8:1
imx8dxl_dwmac_data	dwmac-imx.c	/^static struct imx_dwmac_ops imx8dxl_dwmac_data = {$/;"	v	typeref:struct:imx_dwmac_ops	file:
imx8dxl_set_intf_mode	dwmac-imx.c	/^imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)$/;"	f	typeref:typename:int	file:
imx8mp_dwmac_data	dwmac-imx.c	/^static struct imx_dwmac_ops imx8mp_dwmac_data = {$/;"	v	typeref:struct:imx_dwmac_ops	file:
imx8mp_set_intf_mode	dwmac-imx.c	/^static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)$/;"	f	typeref:typename:int	file:
imx_dwmac_driver	dwmac-imx.c	/^static struct platform_driver imx_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
imx_dwmac_exit	dwmac-imx.c	/^static void imx_dwmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
imx_dwmac_fix_speed	dwmac-imx.c	/^static void imx_dwmac_fix_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
imx_dwmac_init	dwmac-imx.c	/^static int imx_dwmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
imx_dwmac_match	dwmac-imx.c	/^static const struct of_device_id imx_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
imx_dwmac_ops	dwmac-imx.c	/^struct imx_dwmac_ops {$/;"	s	file:
imx_dwmac_parse_dt	dwmac-imx.c	/^imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)$/;"	f	typeref:typename:int	file:
imx_dwmac_probe	dwmac-imx.c	/^static int imx_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
imx_priv_data	dwmac-imx.c	/^struct imx_priv_data {$/;"	s	file:
in_hw	stmmac.h	/^	bool in_hw;$/;"	m	struct:stmmac_tc_entry	typeref:typename:bool
in_use	stmmac.h	/^	bool in_use;$/;"	m	struct:stmmac_tc_entry	typeref:typename:bool
in_use	stmmac.h	/^	int in_use;$/;"	m	struct:stmmac_flow_entry	typeref:typename:int
index	stmmac.h	/^	u32 index;$/;"	m	struct:stmmac_channel	typeref:typename:u32
init	hwif.h	/^	int (*init)(struct stmmac_priv *priv);$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv)
init	hwif.h	/^	void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,$/;"	m	struct:stmmac_mode_ops	typeref:typename:void (*)(void * des,dma_addr_t phy_addr,unsigned int size,unsigned int extend_desc)
init	hwif.h	/^	void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,int atds)
init_chan	hwif.h	/^	void (*init_chan)(void __iomem *ioaddr,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)
init_desc3	hwif.h	/^	void (*init_desc3)(struct dma_desc *p);$/;"	m	struct:stmmac_mode_ops	typeref:typename:void (*)(struct dma_desc * p)
init_desc3	ring_mode.c	/^static void init_desc3(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
init_dma_chain	chain_mode.c	/^static void init_dma_chain(void *des, dma_addr_t phy_addr,$/;"	f	typeref:typename:void	file:
init_dma_desc_rings	stmmac_main.c	/^static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)$/;"	f	typeref:typename:int	file:
init_dma_rx_desc_rings	stmmac_main.c	/^static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)$/;"	f	typeref:typename:int	file:
init_dma_tx_desc_rings	stmmac_main.c	/^static int init_dma_tx_desc_rings(struct net_device *dev)$/;"	f	typeref:typename:int	file:
init_rx_chan	hwif.h	/^	void (*init_rx_chan)(void __iomem *ioaddr,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t phy,u32 chan)
init_rx_desc	hwif.h	/^	void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int disable_rx_ic,int mode,int end,int bfsize)
init_systime	hwif.h	/^	int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);$/;"	m	struct:stmmac_hwtimestamp	typeref:typename:int (*)(void __iomem * ioaddr,u32 sec,u32 nsec)
init_systime	stmmac_hwtstamp.c	/^static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)$/;"	f	typeref:typename:int	file:
init_tx_chan	hwif.h	/^	void (*init_tx_chan)(void __iomem *ioaddr,$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t phy,u32 chan)
init_tx_desc	hwif.h	/^	void (*init_tx_desc)(struct dma_desc *p, int mode, int end);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int mode,int end)
integrated_phy	dwmac-rk.c	/^	bool integrated_phy;$/;"	m	struct:rk_priv_data	typeref:typename:bool	file:
integrated_phy_powerup	dwmac-rk.c	/^	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);$/;"	m	struct:rk_gmac_ops	typeref:typename:void (*)(struct rk_priv_data * bsp_priv)	file:
intel_dwmac	dwmac-intel-plat.c	/^struct intel_dwmac {$/;"	s	file:
intel_dwmac_data	dwmac-intel-plat.c	/^struct intel_dwmac_data {$/;"	s	file:
intel_eth_pci_driver	dwmac-intel.c	/^static struct pci_driver intel_eth_pci_driver = {$/;"	v	typeref:struct:pci_driver	file:
intel_eth_pci_id_table	dwmac-intel.c	/^static const struct pci_device_id intel_eth_pci_id_table[] = {$/;"	v	typeref:typename:const struct pci_device_id[]	file:
intel_eth_pci_probe	dwmac-intel.c	/^static int intel_eth_pci_probe(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
intel_eth_pci_remove	dwmac-intel.c	/^static void intel_eth_pci_remove(struct pci_dev *pdev)$/;"	f	typeref:typename:void	file:
intel_eth_pci_resume	dwmac-intel.c	/^static int __maybe_unused intel_eth_pci_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
intel_eth_pci_suspend	dwmac-intel.c	/^static int __maybe_unused intel_eth_pci_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
intel_eth_plat_driver	dwmac-intel-plat.c	/^static struct platform_driver intel_eth_plat_driver = {$/;"	v	typeref:struct:platform_driver	file:
intel_eth_plat_match	dwmac-intel-plat.c	/^static const struct of_device_id intel_eth_plat_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
intel_eth_plat_probe	dwmac-intel-plat.c	/^static int intel_eth_plat_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
intel_eth_plat_remove	dwmac-intel-plat.c	/^static int intel_eth_plat_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
intel_mgbe_common_data	dwmac-intel.c	/^static int intel_mgbe_common_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
intel_priv_data	dwmac-intel.c	/^struct intel_priv_data {$/;"	s	file:
intel_serdes_powerdown	dwmac-intel.c	/^static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)$/;"	f	typeref:typename:void	file:
intel_serdes_powerup	dwmac-intel.c	/^static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)$/;"	f	typeref:typename:int	file:
inter_frame_gap	dwmac1000.h	/^enum inter_frame_gap {$/;"	g
interface	dwmac-sti.c	/^	phy_interface_t interface;	\/* MII interface *\/$/;"	m	struct:sti_dwmac	typeref:typename:phy_interface_t	file:
interface	dwmac-sunxi.c	/^	phy_interface_t interface;$/;"	m	struct:sunxi_priv_data	typeref:typename:phy_interface_t	file:
internal_phy_powered	dwmac-sun8i.c	/^	bool internal_phy_powered;$/;"	m	struct:sunxi_priv_data	typeref:typename:bool	file:
intf_reg_off	dwmac-imx.c	/^	u32 intf_reg_off;$/;"	m	struct:imx_priv_data	typeref:typename:u32	file:
intf_regmap	dwmac-imx.c	/^	struct regmap *intf_regmap;$/;"	m	struct:imx_priv_data	typeref:struct:regmap *	file:
intr_all_mask	hwif.h	/^	void (*intr_all_mask)(void __iomem *ioaddr);$/;"	m	struct:stmmac_mmc_ops	typeref:typename:void (*)(void __iomem * ioaddr)
ioaddr	stmmac.h	/^	void __iomem *ioaddr;$/;"	m	struct:stmmac_priv	typeref:typename:void __iomem *
iot2040_stmmac_dmi_data	dwmac-intel.c	/^static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {$/;"	v	typeref:typename:const struct stmmac_pci_dmi_data	file:
iot2040_stmmac_func_data	dwmac-intel.c	/^static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {$/;"	v	typeref:typename:const struct stmmac_pci_func_data[]	file:
ip_csum_bypassed	common.h	/^	unsigned long ip_csum_bypassed;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ip_dst	stmmac_selftests.c	/^	u32 ip_dst;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u32	file:
ip_hdr_err	common.h	/^	unsigned long ip_hdr_err;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ip_payload_err	common.h	/^	unsigned long ip_payload_err;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ip_proto	stmmac.h	/^	u8 ip_proto;$/;"	m	struct:stmmac_flow_entry	typeref:typename:u8
ip_src	stmmac_selftests.c	/^	u32 ip_src;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u32	file:
ipc_csum_error	common.h	/^	unsigned long ipc_csum_error;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ipq806x_gmac	dwmac-ipq806x.c	/^struct ipq806x_gmac {$/;"	s	file:
ipq806x_gmac_dwmac_driver	dwmac-ipq806x.c	/^static struct platform_driver ipq806x_gmac_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
ipq806x_gmac_dwmac_match	dwmac-ipq806x.c	/^static const struct of_device_id ipq806x_gmac_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
ipq806x_gmac_fix_mac_speed	dwmac-ipq806x.c	/^static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
ipq806x_gmac_of_parse	dwmac-ipq806x.c	/^static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)$/;"	f	typeref:typename:int	file:
ipq806x_gmac_probe	dwmac-ipq806x.c	/^static int ipq806x_gmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
ipq806x_gmac_set_speed	dwmac-ipq806x.c	/^static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)$/;"	f	typeref:typename:int	file:
ipv4_pkt_rcvd	common.h	/^	unsigned long ipv4_pkt_rcvd;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ipv6_pkt_rcvd	common.h	/^	unsigned long ipv6_pkt_rcvd;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq	stmmac.h	/^	int irq;$/;"	m	struct:stmmac_resources	typeref:typename:int
irq_pcs_ane_n	common.h	/^	unsigned long irq_pcs_ane_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_pcs_link_n	common.h	/^	unsigned long irq_pcs_link_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_pwr_wakeup	dwmac-stm32.c	/^	int irq_pwr_wakeup;$/;"	m	struct:stm32_dwmac	typeref:typename:int	file:
irq_receive_pmt_irq_n	common.h	/^	unsigned long irq_receive_pmt_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_rgmii_n	common.h	/^	unsigned long irq_rgmii_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_rx_path_exit_lpi_mode_n	common.h	/^	unsigned long irq_rx_path_exit_lpi_mode_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_rx_path_in_lpi_mode_n	common.h	/^	unsigned long irq_rx_path_in_lpi_mode_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_tx_path_exit_lpi_mode_n	common.h	/^	unsigned long irq_tx_path_exit_lpi_mode_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_tx_path_in_lpi_mode_n	common.h	/^	unsigned long irq_tx_path_in_lpi_mode_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
irq_wake	stmmac.h	/^	int irq_wake;$/;"	m	struct:stmmac_priv	typeref:typename:int
is_frag	stmmac.h	/^	bool is_frag;$/;"	m	struct:stmmac_tc_entry	typeref:typename:bool
is_jumbo	stmmac.h	/^	bool is_jumbo;$/;"	m	struct:stmmac_tx_info	typeref:typename:bool
is_jumbo_frm	chain_mode.c	/^static unsigned int is_jumbo_frm(int len, int enh_desc)$/;"	f	typeref:typename:unsigned int	file:
is_jumbo_frm	hwif.h	/^	unsigned int (*is_jumbo_frm) (int len, int ehn_desc);$/;"	m	struct:stmmac_mode_ops	typeref:typename:unsigned int (*)(int len,int ehn_desc)
is_jumbo_frm	ring_mode.c	/^static unsigned int is_jumbo_frm(int len, int enh_desc)$/;"	f	typeref:typename:unsigned int	file:
is_l4	stmmac.h	/^	int is_l4;$/;"	m	struct:stmmac_flow_entry	typeref:typename:int
is_last	stmmac.h	/^	bool is_last;$/;"	m	struct:stmmac_tc_entry	typeref:typename:bool
jumbo_frm	chain_mode.c	/^static int jumbo_frm(void *p, struct sk_buff *skb, int csum)$/;"	f	typeref:typename:int	file:
jumbo_frm	hwif.h	/^	int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);$/;"	m	struct:stmmac_mode_ops	typeref:typename:int (*)(void * priv,struct sk_buff * skb,int csum)
jumbo_frm	ring_mode.c	/^static int jumbo_frm(void *p, struct sk_buff *skb, int csum)$/;"	f	typeref:typename:int	file:
key	stmmac.h	/^	u8 key[STMMAC_RSS_HASH_KEY_SIZE];$/;"	m	struct:stmmac_rss	typeref:typename:u8[]
key	stmmac_selftests.c	/^		struct flow_dissector_key_ports key;$/;"	m	struct:__stmmac_test_l4filt::__anon81ae60170108	typeref:struct:flow_dissector_key_ports	file:
kmb_data	dwmac-intel-plat.c	/^static const struct intel_dwmac_data kmb_data = {$/;"	v	typeref:typename:const struct intel_dwmac_data	file:
kmb_eth_fix_mac_speed	dwmac-intel-plat.c	/^static void kmb_eth_fix_mac_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
l3_filter_match	common.h	/^	unsigned long l3_filter_match;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
l3_l4_filter_no_match	common.h	/^	unsigned long l3_l4_filter_no_match;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
l3l4fnum	common.h	/^	unsigned int l3l4fnum;$/;"	m	struct:dma_features	typeref:typename:unsigned int
l4_filter_match	common.h	/^	unsigned long l4_filter_match;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
last_segment	stmmac.h	/^	bool last_segment;$/;"	m	struct:stmmac_tx_info	typeref:typename:bool
lb	stmmac_selftests.c	/^	int lb;$/;"	m	struct:stmmac_test	typeref:typename:int	file:
len	stmmac.h	/^		unsigned int len;$/;"	m	struct:stmmac_rx_queue::__anon84d70a400108	typeref:typename:unsigned int
len	stmmac.h	/^	unsigned len;$/;"	m	struct:stmmac_tx_info	typeref:typename:unsigned
link	common.h	/^	struct mac_link link;$/;"	m	struct:mac_device_info	typeref:struct:mac_link
llc_snap	common.h	/^	llc_snap = 0x4,$/;"	e	enum:rx_frame_status
lock	stmmac.h	/^	spinlock_t lock;$/;"	m	struct:stmmac_channel	typeref:typename:spinlock_t
lock	stmmac.h	/^	struct mutex lock;$/;"	m	struct:stmmac_priv	typeref:struct:mutex
lp_duplex	common.h	/^	unsigned int lp_duplex;$/;"	m	struct:rgmii_adv	typeref:typename:unsigned int
lp_pause	common.h	/^	unsigned int lp_pause;$/;"	m	struct:rgmii_adv	typeref:typename:unsigned int
lpc18xx_dwmac_driver	dwmac-lpc18xx.c	/^static struct platform_driver lpc18xx_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
lpc18xx_dwmac_match	dwmac-lpc18xx.c	/^static const struct of_device_id lpc18xx_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
lpc18xx_dwmac_probe	dwmac-lpc18xx.c	/^static int lpc18xx_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
lpi_irq	dwmac4.h	/^	lpi_irq = 0x00000020,$/;"	e	enum:dwmac4_irq_status
lpi_irq	stmmac.h	/^	int lpi_irq;$/;"	m	struct:stmmac_priv	typeref:typename:int
lpi_irq	stmmac.h	/^	int lpi_irq;$/;"	m	struct:stmmac_resources	typeref:typename:int
m250_div	dwmac-meson8b.c	/^	struct clk_divider	m250_div;$/;"	m	struct:meson8b_dwmac_clk_configs	typeref:struct:clk_divider	file:
m250_mux	dwmac-meson8b.c	/^	struct clk_mux		m250_mux;$/;"	m	struct:meson8b_dwmac_clk_configs	typeref:struct:clk_mux	file:
mac	common.h	/^	const struct stmmac_ops *mac;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_ops *
mac	hwif.c	/^	const void *mac;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
mac	stmmac.h	/^	const char *mac;$/;"	m	struct:stmmac_resources	typeref:typename:const char *
mac_clk_rx	dwmac-rk.c	/^	struct clk *mac_clk_rx;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
mac_clk_tx	dwmac-rk.c	/^	struct clk *mac_clk_tx;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
mac_delay	dwmac-mediatek.c	/^	struct mac_delay_struct mac_delay;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:struct:mac_delay_struct	file:
mac_delay_struct	dwmac-mediatek.c	/^struct mac_delay_struct {$/;"	s	file:
mac_device_info	common.h	/^struct mac_device_info {$/;"	s
mac_errors	common.h	/^	unsigned long mac_errors[32];$/;"	m	struct:stmmac_safety_stats	typeref:typename:unsigned long[32]
mac_gmii_rx_proto_engine	common.h	/^	unsigned long mac_gmii_rx_proto_engine;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_gmii_tx_proto_engine	common.h	/^	unsigned long mac_gmii_tx_proto_engine;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_link	common.h	/^struct mac_link {$/;"	s
mac_rgmii_txclk_auto_adj	dwmac-imx.c	/^	bool mac_rgmii_txclk_auto_adj;$/;"	m	struct:imx_dwmac_ops	typeref:typename:bool	file:
mac_rx_frame_ctrl_fifo	common.h	/^	unsigned long mac_rx_frame_ctrl_fifo;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_tx_frame_ctrl_idle	common.h	/^	unsigned long mac_tx_frame_ctrl_idle;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_tx_frame_ctrl_pause	common.h	/^	unsigned long mac_tx_frame_ctrl_pause;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_tx_frame_ctrl_wait	common.h	/^	unsigned long mac_tx_frame_ctrl_wait;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_tx_frame_ctrl_xfer	common.h	/^	unsigned long mac_tx_frame_ctrl_xfer;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mac_tx_in_pause	common.h	/^	unsigned long mac_tx_in_pause;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
magic	stmmac_selftests.c	/^	__be64 magic;$/;"	m	struct:stmmachdr	typeref:typename:__be64	file:
magic_frame	dwmac1000.h	/^	magic_frame = 0x00000020,$/;"	e	enum:power_event
magic_frame	dwmac4.h	/^	magic_frame = 0x00000020,$/;"	e	enum:power_event
magic_pkt_en	dwmac1000.h	/^	magic_pkt_en = 0x00000002,$/;"	e	enum:power_event
magic_pkt_en	dwmac4.h	/^	magic_pkt_en = 0x00000002,$/;"	e	enum:power_event
map_as_page	stmmac.h	/^	bool map_as_page;$/;"	m	struct:stmmac_tx_info	typeref:typename:bool
map_mtl_to_dma	hwif.h	/^	void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 queue,u32 chan)
mask	stmmac_selftests.c	/^		struct flow_dissector_key_ports mask;$/;"	m	struct:__stmmac_test_l4filt::__anon81ae60170208	typeref:struct:flow_dissector_key_ports	file:
match_data	stmmac.h	/^		u32 match_data;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u32
match_en	stmmac.h	/^		u32 match_en;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u32
max_size	stmmac_selftests.c	/^	int max_size;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
mbps_1000	common.h	/^	unsigned int mbps_1000;$/;"	m	struct:dma_features	typeref:typename:unsigned int
mbps_10_100	common.h	/^	unsigned int mbps_10_100;$/;"	m	struct:dma_features	typeref:typename:unsigned int
mcast_bits_log2	common.h	/^	unsigned int mcast_bits_log2;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
mdio_adhoc_addr	dwmac-intel.c	/^	int mdio_adhoc_addr;	\/* mdio address for serdes & etc *\/$/;"	m	struct:intel_priv_data	typeref:typename:int	file:
mdio_mux_syscon_switch_fn	dwmac-sun8i.c	/^static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,$/;"	f	typeref:typename:int	file:
mediatek_dwmac_clk_init	dwmac-mediatek.c	/^static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:int	file:
mediatek_dwmac_config_dt	dwmac-mediatek.c	/^static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:int	file:
mediatek_dwmac_driver	dwmac-mediatek.c	/^static struct platform_driver mediatek_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
mediatek_dwmac_exit	dwmac-mediatek.c	/^static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
mediatek_dwmac_init	dwmac-mediatek.c	/^static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
mediatek_dwmac_match	dwmac-mediatek.c	/^static const struct of_device_id mediatek_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
mediatek_dwmac_plat_data	dwmac-mediatek.c	/^struct mediatek_dwmac_plat_data {$/;"	s	file:
mediatek_dwmac_probe	dwmac-mediatek.c	/^static int mediatek_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
mediatek_dwmac_variant	dwmac-mediatek.c	/^struct mediatek_dwmac_variant {$/;"	s	file:
meson6_dwmac_driver	dwmac-meson.c	/^static struct platform_driver meson6_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
meson6_dwmac_fix_mac_speed	dwmac-meson.c	/^static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
meson6_dwmac_match	dwmac-meson.c	/^static const struct of_device_id meson6_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
meson6_dwmac_probe	dwmac-meson.c	/^static int meson6_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
meson8b_devm_clk_prepare_enable	dwmac-meson8b.c	/^static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,$/;"	f	typeref:typename:int	file:
meson8b_dwmac	dwmac-meson8b.c	/^struct meson8b_dwmac {$/;"	s	file:
meson8b_dwmac_clk_configs	dwmac-meson8b.c	/^struct meson8b_dwmac_clk_configs {$/;"	s	file:
meson8b_dwmac_data	dwmac-meson8b.c	/^static const struct meson8b_dwmac_data meson8b_dwmac_data = {$/;"	v	typeref:typename:const struct meson8b_dwmac_data	file:
meson8b_dwmac_data	dwmac-meson8b.c	/^struct meson8b_dwmac_data {$/;"	s	file:
meson8b_dwmac_driver	dwmac-meson8b.c	/^static struct platform_driver meson8b_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
meson8b_dwmac_mask_bits	dwmac-meson8b.c	/^static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,$/;"	f	typeref:typename:void	file:
meson8b_dwmac_match	dwmac-meson8b.c	/^static const struct of_device_id meson8b_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
meson8b_dwmac_probe	dwmac-meson8b.c	/^static int meson8b_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
meson8b_dwmac_register_clk	dwmac-meson8b.c	/^static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,$/;"	f	typeref:struct:clk *	file:
meson8b_init_prg_eth	dwmac-meson8b.c	/^static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
meson8b_init_rgmii_tx_clk	dwmac-meson8b.c	/^static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
meson8b_set_phy_mode	dwmac-meson8b.c	/^static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
meson_axg_dwmac_data	dwmac-meson8b.c	/^static const struct meson8b_dwmac_data meson_axg_dwmac_data = {$/;"	v	typeref:typename:const struct meson8b_dwmac_data	file:
meson_axg_set_phy_mode	dwmac-meson8b.c	/^static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
meson_dwmac	dwmac-meson.c	/^struct meson_dwmac {$/;"	s	file:
mii	common.h	/^	struct mii_regs mii;	\/* MII register Addresses *\/$/;"	m	struct:mac_device_info	typeref:struct:mii_regs
mii	stmmac.h	/^	struct mii_bus *mii;$/;"	m	struct:stmmac_priv	typeref:struct:mii_bus *
mii_irq	stmmac.h	/^	int mii_irq[PHY_MAX_ADDR];$/;"	m	struct:stmmac_priv	typeref:typename:int[]
mii_regs	common.h	/^struct mii_regs {$/;"	s
min_id	hwif.c	/^	u32 min_id;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:u32	file:
mmc	common.h	/^	const struct stmmac_mmc_ops *mmc;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_mmc_ops *
mmc	hwif.c	/^	const void *mmc;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
mmc	stmmac.h	/^	struct stmmac_counters mmc;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_counters
mmc_irq	dwmac4.h	/^	mmc_irq = 0x00000100,$/;"	e	enum:dwmac4_irq_status
mmc_off	hwif.h	/^	u32 mmc_off;$/;"	m	struct:stmmac_regs_off	typeref:typename:u32
mmc_rx_1024_to_max_octets_gb	mmc.h	/^	unsigned int mmc_rx_1024_to_max_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_128_to_255_octets_gb	mmc.h	/^	unsigned int mmc_rx_128_to_255_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_256_to_511_octets_gb	mmc.h	/^	unsigned int mmc_rx_256_to_511_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_512_to_1023_octets_gb	mmc.h	/^	unsigned int mmc_rx_512_to_1023_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_64_octets_gb	mmc.h	/^	unsigned int mmc_rx_64_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_65_to_127_octets_gb	mmc.h	/^	unsigned int mmc_rx_65_to_127_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_align_error	mmc.h	/^	unsigned int mmc_rx_align_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_autofrangetype	mmc.h	/^	unsigned int mmc_rx_autofrangetype;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_broadcastframe_g	mmc.h	/^	unsigned int mmc_rx_broadcastframe_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_crc_error	mmc.h	/^	unsigned int mmc_rx_crc_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_csum_offload_irq	dwmac4.h	/^	mmc_rx_csum_offload_irq = 0x00000800,$/;"	e	enum:dwmac4_irq_status
mmc_rx_csum_offload_irq_n	common.h	/^	unsigned long mmc_rx_csum_offload_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mmc_rx_fifo_overflow	mmc.h	/^	unsigned int mmc_rx_fifo_overflow;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_fpe_fragment_cntr	mmc.h	/^	unsigned int mmc_rx_fpe_fragment_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_framecount_gb	mmc.h	/^	unsigned int mmc_rx_framecount_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_icmp_err	mmc.h	/^	unsigned int mmc_rx_icmp_err;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_icmp_err_octets	mmc.h	/^	unsigned int mmc_rx_icmp_err_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_icmp_gd	mmc.h	/^	unsigned int mmc_rx_icmp_gd;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_icmp_gd_octets	mmc.h	/^	unsigned int mmc_rx_icmp_gd_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipc_intr	mmc.h	/^	unsigned int mmc_rx_ipc_intr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipc_intr_mask	mmc.h	/^	unsigned int mmc_rx_ipc_intr_mask;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_frag	mmc.h	/^	unsigned int mmc_rx_ipv4_frag;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_frag_octets	mmc.h	/^	unsigned int mmc_rx_ipv4_frag_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_gd	mmc.h	/^	unsigned int mmc_rx_ipv4_gd;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_gd_octets	mmc.h	/^	unsigned int mmc_rx_ipv4_gd_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_hderr	mmc.h	/^	unsigned int mmc_rx_ipv4_hderr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_hderr_octets	mmc.h	/^	unsigned int mmc_rx_ipv4_hderr_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_nopay	mmc.h	/^	unsigned int mmc_rx_ipv4_nopay;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_nopay_octets	mmc.h	/^	unsigned int mmc_rx_ipv4_nopay_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_udsbl	mmc.h	/^	unsigned int mmc_rx_ipv4_udsbl;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv4_udsbl_octets	mmc.h	/^	unsigned int mmc_rx_ipv4_udsbl_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_gd	mmc.h	/^	unsigned int mmc_rx_ipv6_gd;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_gd_octets	mmc.h	/^	unsigned int mmc_rx_ipv6_gd_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_hderr	mmc.h	/^	unsigned int mmc_rx_ipv6_hderr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_hderr_octets	mmc.h	/^	unsigned int mmc_rx_ipv6_hderr_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_nopay	mmc.h	/^	unsigned int mmc_rx_ipv6_nopay;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_ipv6_nopay_octets	mmc.h	/^	unsigned int mmc_rx_ipv6_nopay_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_irq	dwmac4.h	/^	mmc_rx_irq = 0x00000200,$/;"	e	enum:dwmac4_irq_status
mmc_rx_irq_n	common.h	/^	unsigned long mmc_rx_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mmc_rx_jabber_error	mmc.h	/^	unsigned int mmc_rx_jabber_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_length_error	mmc.h	/^	unsigned int mmc_rx_length_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_multicastframe_g	mmc.h	/^	unsigned int mmc_rx_multicastframe_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_octetcount_g	mmc.h	/^	unsigned int mmc_rx_octetcount_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_octetcount_gb	mmc.h	/^	unsigned int mmc_rx_octetcount_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_oversize_g	mmc.h	/^	unsigned int mmc_rx_oversize_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_packet_assembly_err_cntr	mmc.h	/^	unsigned int mmc_rx_packet_assembly_err_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_packet_assembly_ok_cntr	mmc.h	/^	unsigned int mmc_rx_packet_assembly_ok_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_packet_smd_err_cntr	mmc.h	/^	unsigned int mmc_rx_packet_smd_err_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_pause_frames	mmc.h	/^	unsigned int mmc_rx_pause_frames;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_run_error	mmc.h	/^	unsigned int mmc_rx_run_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_tcp_err	mmc.h	/^	unsigned int mmc_rx_tcp_err;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_tcp_err_octets	mmc.h	/^	unsigned int mmc_rx_tcp_err_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_tcp_gd	mmc.h	/^	unsigned int mmc_rx_tcp_gd;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_tcp_gd_octets	mmc.h	/^	unsigned int mmc_rx_tcp_gd_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_udp_err	mmc.h	/^	unsigned int mmc_rx_udp_err;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_udp_err_octets	mmc.h	/^	unsigned int mmc_rx_udp_err_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_udp_gd	mmc.h	/^	unsigned int mmc_rx_udp_gd;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_udp_gd_octets	mmc.h	/^	unsigned int mmc_rx_udp_gd_octets;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_undersize_g	mmc.h	/^	unsigned int mmc_rx_undersize_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_unicast_g	mmc.h	/^	unsigned int mmc_rx_unicast_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_vlan_frames_gb	mmc.h	/^	unsigned int mmc_rx_vlan_frames_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_rx_watchdog_error	mmc.h	/^	unsigned int mmc_rx_watchdog_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_1024_to_max_octets_gb	mmc.h	/^	unsigned int mmc_tx_1024_to_max_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_128_to_255_octets_gb	mmc.h	/^	unsigned int mmc_tx_128_to_255_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_256_to_511_octets_gb	mmc.h	/^	unsigned int mmc_tx_256_to_511_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_512_to_1023_octets_gb	mmc.h	/^	unsigned int mmc_tx_512_to_1023_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_64_octets_gb	mmc.h	/^	unsigned int mmc_tx_64_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_65_to_127_octets_gb	mmc.h	/^	unsigned int mmc_tx_65_to_127_octets_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_broadcast_gb	mmc.h	/^	unsigned int mmc_tx_broadcast_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_broadcastframe_g	mmc.h	/^	unsigned int mmc_tx_broadcastframe_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_carrier_error	mmc.h	/^	unsigned int mmc_tx_carrier_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_deferred	mmc.h	/^	unsigned int mmc_tx_deferred;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_excessdef	mmc.h	/^	unsigned int mmc_tx_excessdef;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_exesscol	mmc.h	/^	unsigned int mmc_tx_exesscol;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_fpe_fragment_cntr	mmc.h	/^	unsigned int mmc_tx_fpe_fragment_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_framecount_g	mmc.h	/^	unsigned int mmc_tx_framecount_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_framecount_gb	mmc.h	/^	unsigned int mmc_tx_framecount_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_hold_req_cntr	mmc.h	/^	unsigned int mmc_tx_hold_req_cntr;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_irq	dwmac4.h	/^	mmc_tx_irq = 0x00000400,$/;"	e	enum:dwmac4_irq_status
mmc_tx_irq_n	common.h	/^	unsigned long mmc_tx_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mmc_tx_latecol	mmc.h	/^	unsigned int mmc_tx_latecol;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_multicast_gb	mmc.h	/^	unsigned int mmc_tx_multicast_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_multicastframe_g	mmc.h	/^	unsigned int mmc_tx_multicastframe_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_multicol_g	mmc.h	/^	unsigned int mmc_tx_multicol_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_octetcount_g	mmc.h	/^	unsigned int mmc_tx_octetcount_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_octetcount_gb	mmc.h	/^	unsigned int mmc_tx_octetcount_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_pause_frame	mmc.h	/^	unsigned int mmc_tx_pause_frame;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_singlecol_g	mmc.h	/^	unsigned int mmc_tx_singlecol_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_underflow_error	mmc.h	/^	unsigned int mmc_tx_underflow_error;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_unicast_gb	mmc.h	/^	unsigned int mmc_tx_unicast_gb;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmc_tx_vlan_frame_g	mmc.h	/^	unsigned int mmc_tx_vlan_frame_g;$/;"	m	struct:stmmac_counters	typeref:typename:unsigned int
mmcaddr	stmmac.h	/^	void __iomem *mmcaddr;$/;"	m	struct:stmmac_priv	typeref:typename:void __iomem *
mmtl_fifo_ctrl	common.h	/^	unsigned long mmtl_fifo_ctrl;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mode	common.h	/^	const struct stmmac_mode_ops *mode;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_mode_ops *
mode	hwif.c	/^	const void *mode;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
mode	stmmac.h	/^	unsigned int mode;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
mode_reg	dwmac-stm32.c	/^	u32 mode_reg;		 \/* MAC glue-logic mode register *\/$/;"	m	struct:stm32_dwmac	typeref:typename:u32	file:
msg_enable	stmmac.h	/^	u32 msg_enable;$/;"	m	struct:stmmac_priv	typeref:typename:u32
mss	stmmac.h	/^	u32 mss;$/;"	m	struct:stmmac_tx_queue	typeref:typename:u32
mt2712_delay_ps2stage	dwmac-mediatek.c	/^static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:void	file:
mt2712_delay_stage2ps	dwmac-mediatek.c	/^static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:void	file:
mt2712_dwmac_clk_l	dwmac-mediatek.c	/^static const char * const mt2712_dwmac_clk_l[] = {$/;"	v	typeref:typename:const char * const[]	file:
mt2712_gmac_variant	dwmac-mediatek.c	/^static const struct mediatek_dwmac_variant mt2712_gmac_variant = {$/;"	v	typeref:typename:const struct mediatek_dwmac_variant	file:
mt2712_set_delay	dwmac-mediatek.c	/^static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:int	file:
mt2712_set_interface	dwmac-mediatek.c	/^static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)$/;"	f	typeref:typename:int	file:
mtl_errors	common.h	/^	unsigned long mtl_errors[32];$/;"	m	struct:stmmac_safety_stats	typeref:typename:unsigned long[32]
mtl_rx_fifo_ctrl_active	common.h	/^	unsigned long mtl_rx_fifo_ctrl_active;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_fill_above_thresh	common.h	/^	unsigned long mtl_rx_fifo_fill_above_thresh;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_fill_below_thresh	common.h	/^	unsigned long mtl_rx_fifo_fill_below_thresh;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_fill_level_empty	common.h	/^	unsigned long mtl_rx_fifo_fill_level_empty;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_fill_level_full	common.h	/^	unsigned long mtl_rx_fifo_fill_level_full;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_read_ctrl_flush	common.h	/^	unsigned long mtl_rx_fifo_read_ctrl_flush;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_read_ctrl_idle	common.h	/^	unsigned long mtl_rx_fifo_read_ctrl_idle;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_read_ctrl_read_data	common.h	/^	unsigned long mtl_rx_fifo_read_ctrl_read_data;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_rx_fifo_read_ctrl_status	common.h	/^	unsigned long mtl_rx_fifo_read_ctrl_status;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_fifo_not_empty	common.h	/^	unsigned long mtl_tx_fifo_not_empty;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_fifo_read_ctrl_idle	common.h	/^	unsigned long mtl_tx_fifo_read_ctrl_idle;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_fifo_read_ctrl_read	common.h	/^	unsigned long mtl_tx_fifo_read_ctrl_read;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_fifo_read_ctrl_wait	common.h	/^	unsigned long mtl_tx_fifo_read_ctrl_wait;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_fifo_read_ctrl_write	common.h	/^	unsigned long mtl_tx_fifo_read_ctrl_write;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
mtl_tx_status_fifo_full	common.h	/^	unsigned long mtl_tx_status_fifo_full;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
multi_addr	common.h	/^	unsigned int multi_addr;$/;"	m	struct:dma_features	typeref:typename:unsigned int
multicast_filter_bins	common.h	/^	unsigned int multicast_filter_bins;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
mux_handle	dwmac-sun8i.c	/^	void *mux_handle;$/;"	m	struct:sunxi_priv_data	typeref:typename:void *	file:
name	stmmac_selftests.c	/^	char name[ETH_GSTRING_LEN];$/;"	m	struct:stmmac_test	typeref:typename:char[]	file:
napi_poll	common.h	/^	unsigned long napi_poll;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
nc	stmmac.h	/^		u8 nc:1;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8:1
ndesc_clear	norm_desc.c	/^static void ndesc_clear(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
ndesc_display_ring	norm_desc.c	/^static void ndesc_display_ring(void *head, unsigned int size, bool rx,$/;"	f	typeref:typename:void	file:
ndesc_enable_tx_timestamp	norm_desc.c	/^static void ndesc_enable_tx_timestamp(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
ndesc_end_tx_desc_on_ring	descs_com.h	/^static inline void ndesc_end_tx_desc_on_ring(struct dma_desc *p, int end)$/;"	f	typeref:typename:void
ndesc_get_addr	norm_desc.c	/^static void ndesc_get_addr(struct dma_desc *p, unsigned int *addr)$/;"	f	typeref:typename:void	file:
ndesc_get_rx_frame_len	norm_desc.c	/^static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)$/;"	f	typeref:typename:int	file:
ndesc_get_rx_status	norm_desc.c	/^static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
ndesc_get_rx_timestamp_status	norm_desc.c	/^static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats)$/;"	f	typeref:typename:int	file:
ndesc_get_timestamp	norm_desc.c	/^static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts)$/;"	f	typeref:typename:void	file:
ndesc_get_tx_len	norm_desc.c	/^static int ndesc_get_tx_len(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
ndesc_get_tx_ls	norm_desc.c	/^static int ndesc_get_tx_ls(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
ndesc_get_tx_owner	norm_desc.c	/^static int ndesc_get_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
ndesc_get_tx_status	norm_desc.c	/^static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,$/;"	f	typeref:typename:int	file:
ndesc_get_tx_timestamp_status	norm_desc.c	/^static int ndesc_get_tx_timestamp_status(struct dma_desc *p)$/;"	f	typeref:typename:int	file:
ndesc_init_rx_desc	norm_desc.c	/^static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,$/;"	f	typeref:typename:void	file:
ndesc_init_tx_desc	norm_desc.c	/^static void ndesc_init_tx_desc(struct dma_desc *p, int mode, int end)$/;"	f	typeref:typename:void	file:
ndesc_ops	norm_desc.c	/^const struct stmmac_desc_ops ndesc_ops = {$/;"	v	typeref:typename:const struct stmmac_desc_ops
ndesc_prepare_tx_desc	norm_desc.c	/^static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,$/;"	f	typeref:typename:void	file:
ndesc_release_tx_desc	norm_desc.c	/^static void ndesc_release_tx_desc(struct dma_desc *p, int mode)$/;"	f	typeref:typename:void	file:
ndesc_rx_set_on_chain	descs_com.h	/^static inline void ndesc_rx_set_on_chain(struct dma_desc *p, int end)$/;"	f	typeref:typename:void
ndesc_rx_set_on_ring	descs_com.h	/^static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)$/;"	f	typeref:typename:void
ndesc_set_addr	norm_desc.c	/^static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)$/;"	f	typeref:typename:void	file:
ndesc_set_rx_owner	norm_desc.c	/^static void ndesc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)$/;"	f	typeref:typename:void	file:
ndesc_set_tx_ic	norm_desc.c	/^static void ndesc_set_tx_ic(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
ndesc_set_tx_owner	norm_desc.c	/^static void ndesc_set_tx_owner(struct dma_desc *p)$/;"	f	typeref:typename:void	file:
ndesc_tx_set_on_chain	descs_com.h	/^static inline void ndesc_tx_set_on_chain(struct dma_desc *p)$/;"	f	typeref:typename:void
nfuncs	dwmac-intel.c	/^	size_t nfuncs;$/;"	m	struct:stmmac_pci_dmi_data	typeref:typename:size_t	file:
no_ptp_rx_msg_type_ext	common.h	/^	unsigned long no_ptp_rx_msg_type_ext;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
norm_set_tx_desc_len_on_chain	descs_com.h	/^static inline void norm_set_tx_desc_len_on_chain(struct dma_desc *p, int len)$/;"	f	typeref:typename:void
norm_set_tx_desc_len_on_ring	descs_com.h	/^static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len)$/;"	f	typeref:typename:void
normal_irq_n	common.h	/^	unsigned long normal_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
np	dwmac-mediatek.c	/^	struct device_node *np;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:struct:device_node *	file:
nss_common	dwmac-ipq806x.c	/^	struct regmap *nss_common;$/;"	m	struct:ipq806x_gmac	typeref:struct:regmap *	file:
num_clks	dwmac-mediatek.c	/^	int num_clks;$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:int	file:
num_clks_to_config	dwmac-mediatek.c	/^	int num_clks_to_config;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:typename:int	file:
num_por	dwmac-qcom-ethqos.c	/^	unsigned int num_por;$/;"	m	struct:ethqos_emac_driver_data	typeref:typename:unsigned int	file:
num_por	dwmac-qcom-ethqos.c	/^	unsigned int num_por;$/;"	m	struct:qcom_ethqos	typeref:typename:unsigned int	file:
num_vlan	common.h	/^	unsigned int num_vlan;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
number_rx_channel	common.h	/^	unsigned int number_rx_channel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
number_rx_queues	common.h	/^	unsigned int number_rx_queues;$/;"	m	struct:dma_features	typeref:typename:unsigned int
number_tx_channel	common.h	/^	unsigned int number_tx_channel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
number_tx_queues	common.h	/^	unsigned int number_tx_queues;$/;"	m	struct:dma_features	typeref:typename:unsigned int
offset	dwmac-qcom-ethqos.c	/^	unsigned int offset;$/;"	m	struct:ethqos_emac_por	typeref:typename:unsigned int	file:
ok	stmmac_selftests.c	/^	int ok;$/;"	m	struct:stmmac_test_priv	typeref:typename:int	file:
ok_index	stmmac.h	/^		u8 ok_index;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8
ops	dwmac-imx.c	/^	const struct imx_dwmac_ops *ops;$/;"	m	struct:imx_priv_data	typeref:typename:const struct imx_dwmac_ops *	file:
ops	dwmac-rk.c	/^	const struct rk_gmac_ops *ops;$/;"	m	struct:rk_priv_data	typeref:typename:const struct rk_gmac_ops *	file:
ops	dwmac-socfpga.c	/^	const struct socfpga_dwmac_ops *ops;$/;"	m	struct:socfpga_dwmac	typeref:typename:const struct socfpga_dwmac_ops *	file:
ops	dwmac-stm32.c	/^	const struct stm32_ops *ops;$/;"	m	struct:stm32_dwmac	typeref:typename:const struct stm32_ops *	file:
overflow_error	common.h	/^	unsigned long overflow_error;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
oxnas_dwmac	dwmac-oxnas.c	/^struct oxnas_dwmac {$/;"	s	file:
oxnas_dwmac_driver	dwmac-oxnas.c	/^static struct platform_driver oxnas_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
oxnas_dwmac_exit	dwmac-oxnas.c	/^static void oxnas_dwmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
oxnas_dwmac_init	dwmac-oxnas.c	/^static int oxnas_dwmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
oxnas_dwmac_match	dwmac-oxnas.c	/^static const struct of_device_id oxnas_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
oxnas_dwmac_probe	dwmac-oxnas.c	/^static int oxnas_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
packet	stmmac_selftests.c	/^	struct stmmac_packet_attrs *packet;$/;"	m	struct:stmmac_test_priv	typeref:struct:stmmac_packet_attrs *	file:
packets_types	common.h	/^enum packets_types {$/;"	g
page	stmmac.h	/^	struct page *page;$/;"	m	struct:stmmac_rx_buffer	typeref:struct:page *
page_pool	stmmac.h	/^	struct page_pool *page_pool;$/;"	m	struct:stmmac_rx_queue	typeref:struct:page_pool *
parse_data	dwmac-stm32.c	/^	int (*parse_data)(struct stm32_dwmac *dwmac,$/;"	m	struct:stm32_ops	typeref:typename:int (*)(struct stm32_dwmac * dwmac,struct device * dev)	file:
pause	common.h	/^	unsigned int pause;$/;"	m	struct:rgmii_adv	typeref:typename:unsigned int
pause	stmmac.h	/^	unsigned int pause;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
pause	stmmac_main.c	/^static int pause = PAUSE_TIME;$/;"	v	typeref:typename:int	file:
pclk_mac	dwmac-rk.c	/^	struct clk *pclk_mac;$/;"	m	struct:rk_priv_data	typeref:struct:clk *	file:
pcs	common.h	/^	unsigned int pcs;$/;"	m	struct:dma_features	typeref:typename:unsigned int
pcs	common.h	/^	unsigned int pcs;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
pcs	dwmac-socfpga.c	/^	struct tse_pcs pcs;$/;"	m	struct:socfpga_dwmac	typeref:struct:tse_pcs	file:
pcs_ctrl_ane	hwif.h	/^	void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool ane,bool srgmi_ral,bool loopback)
pcs_duplex	common.h	/^	unsigned long pcs_duplex;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
pcs_get_adv_lp	hwif.h	/^	void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct rgmii_adv * adv)
pcs_link	common.h	/^	unsigned long pcs_link;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
pcs_link_timer_callback	altr_tse_pcs.c	/^static void pcs_link_timer_callback(struct tse_pcs *pcs)$/;"	f	typeref:typename:void	file:
pcs_rane	hwif.h	/^	void (*pcs_rane)(void __iomem *ioaddr, bool restart);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool restart)
pcs_speed	common.h	/^	unsigned long pcs_speed;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
pcsr	common.h	/^	void __iomem *pcsr;     \/* vpointer to device CSRs *\/$/;"	m	struct:mac_device_info	typeref:typename:void __iomem *
pdev	dwmac-ipq806x.c	/^	struct platform_device *pdev;$/;"	m	struct:ipq806x_gmac	typeref:struct:platform_device *	file:
pdev	dwmac-qcom-ethqos.c	/^	struct platform_device *pdev;$/;"	m	struct:qcom_ethqos	typeref:struct:platform_device *	file:
pdev	dwmac-rk.c	/^	struct platform_device *pdev;$/;"	m	struct:rk_priv_data	typeref:struct:platform_device *	file:
peri_regmap	dwmac-mediatek.c	/^	struct regmap *peri_regmap;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:struct:regmap *	file:
period	stmmac.h	/^	struct timespec64 period;$/;"	m	struct:stmmac_pps_cfg	typeref:struct:timespec64
phy_addr	dwmac-intel.c	/^	int phy_addr;$/;"	m	struct:stmmac_pci_func_data	typeref:typename:int	file:
phy_eee_wakeup_error_n	common.h	/^	unsigned long phy_eee_wakeup_error_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
phy_iface	dwmac-rk.c	/^	phy_interface_t phy_iface;$/;"	m	struct:rk_priv_data	typeref:typename:phy_interface_t	file:
phy_intf_sel	dwmac-anarion.c	/^	uint32_t phy_intf_sel;$/;"	m	struct:anarion_gmac	typeref:typename:uint32_t	file:
phy_intf_sels	dwmac-sti.c	/^static u32 phy_intf_sels[] = {$/;"	v	typeref:typename:u32[]	file:
phy_mode	dwmac-ipq806x.c	/^	phy_interface_t phy_mode;$/;"	m	struct:ipq806x_gmac	typeref:typename:phy_interface_t	file:
phy_mode	dwmac-mediatek.c	/^	phy_interface_t phy_mode;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:typename:phy_interface_t	file:
phy_mode	dwmac-meson8b.c	/^	phy_interface_t			phy_mode;$/;"	m	struct:meson8b_dwmac	typeref:typename:phy_interface_t	file:
phy_power_on	dwmac-rk.c	/^static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)$/;"	f	typeref:typename:int	file:
phy_reset	dwmac-rk.c	/^	struct reset_control *phy_reset;$/;"	m	struct:rk_priv_data	typeref:struct:reset_control *	file:
phyaddr	stmmac_main.c	/^static int phyaddr = -1;$/;"	v	typeref:typename:int	file:
phylink	stmmac.h	/^	struct phylink *phylink;$/;"	m	struct:stmmac_priv	typeref:struct:phylink *
phylink_config	stmmac.h	/^	struct phylink_config phylink_config;$/;"	m	struct:stmmac_priv	typeref:struct:phylink_config
plat	stmmac.h	/^	struct plat_stmmacenet_data *plat;$/;"	m	struct:stmmac_priv	typeref:struct:plat_stmmacenet_data *
plat_dat	dwmac-imx.c	/^	struct plat_stmmacenet_data *plat_dat;$/;"	m	struct:imx_priv_data	typeref:struct:plat_stmmacenet_data *	file:
pmt	common.h	/^	unsigned int pmt;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
pmt	hwif.h	/^	void (*pmt)(struct mac_device_info *hw, unsigned long mode);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,unsigned long mode)
pmt_irq	dwmac4.h	/^	pmt_irq = 0x00000010,$/;"	e	enum:dwmac4_irq_status
pmt_magic_frame	common.h	/^	unsigned int pmt_magic_frame;$/;"	m	struct:dma_features	typeref:typename:unsigned int
pmt_remote_wake_up	common.h	/^	unsigned int pmt_remote_wake_up;$/;"	m	struct:dma_features	typeref:typename:unsigned int
pointer_reset	dwmac1000.h	/^	pointer_reset = 0x80000000,$/;"	e	enum:power_event
pointer_reset	dwmac4.h	/^	pointer_reset =	0x80000000,$/;"	e	enum:power_event
por	dwmac-qcom-ethqos.c	/^	const struct ethqos_emac_por *por;$/;"	m	struct:ethqos_emac_driver_data	typeref:typename:const struct ethqos_emac_por *	file:
por	dwmac-qcom-ethqos.c	/^	const struct ethqos_emac_por *por;$/;"	m	struct:qcom_ethqos	typeref:typename:const struct ethqos_emac_por *	file:
power_down	dwmac1000.h	/^	power_down = 0x00000001,$/;"	e	enum:power_event
power_down	dwmac4.h	/^	power_down = 0x00000001,$/;"	e	enum:power_event
power_event	dwmac1000.h	/^enum power_event {$/;"	g
power_event	dwmac4.h	/^enum power_event {$/;"	g
pps	stmmac.h	/^	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_pps_cfg[]
pps_out_num	common.h	/^	unsigned int pps_out_num;$/;"	m	struct:dma_features	typeref:typename:unsigned int
prepare_tso_tx_desc	hwif.h	/^	void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int is_fs,int len1,int len2,bool tx_own,bool ls,unsigned int tcphdrlen,unsigned int tcppayloadlen)
prepare_tx_desc	hwif.h	/^	void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int is_fs,int len,bool csum_flag,int mode,bool tx_own,bool ls,unsigned int tot_pkt_len)
print_pkt	stmmac_main.c	/^static void print_pkt(unsigned char *buf, int len)$/;"	f	typeref:typename:void	file:
prio	stmmac.h	/^	u32 prio;$/;"	m	struct:stmmac_tc_entry	typeref:typename:u32
priv_data	stmmac.h	/^	struct stmmac_priv *priv_data;$/;"	m	struct:stmmac_channel	typeref:struct:stmmac_priv *
priv_data	stmmac.h	/^	struct stmmac_priv *priv_data;$/;"	m	struct:stmmac_rx_queue	typeref:struct:stmmac_priv *
priv_data	stmmac.h	/^	struct stmmac_priv *priv_data;$/;"	m	struct:stmmac_tx_queue	typeref:struct:stmmac_priv *
probe	dwmac-dwc-qos-eth.c	/^	void *(*probe)(struct platform_device *pdev,$/;"	m	struct:dwc_eth_dwmac_data	typeref:typename:void * (*)(struct platform_device * pdev,struct plat_stmmacenet_data * data,struct stmmac_resources * res)	file:
prog_mtl_rx_algorithms	hwif.h	/^	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 rx_alg)
prog_mtl_tx_algorithms	hwif.h	/^	void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 tx_alg)
promisc	common.h	/^	unsigned int promisc;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
ps	common.h	/^	unsigned int ps;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
pt	stmmac_selftests.c	/^	struct packet_type pt;$/;"	m	struct:stmmac_test_priv	typeref:struct:packet_type	file:
ptp	common.h	/^	const struct stmmac_hwtimestamp *ptp;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_hwtimestamp *
ptp_clock	stmmac.h	/^	struct ptp_clock *ptp_clock;$/;"	m	struct:stmmac_priv	typeref:struct:ptp_clock *
ptp_clock_ops	stmmac.h	/^	struct ptp_clock_info ptp_clock_ops;$/;"	m	struct:stmmac_priv	typeref:struct:ptp_clock_info
ptp_frame_type	common.h	/^	unsigned long ptp_frame_type;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_lock	stmmac.h	/^	spinlock_t ptp_lock;$/;"	m	struct:stmmac_priv	typeref:typename:spinlock_t
ptp_off	hwif.h	/^	u32 ptp_off;$/;"	m	struct:stmmac_regs_off	typeref:typename:u32
ptp_ref_clk_rate	dwmac-intel-plat.c	/^	unsigned long ptp_ref_clk_rate;$/;"	m	struct:intel_dwmac_data	typeref:typename:unsigned long	file:
ptp_rx_msg_pkt_reserved_type	common.h	/^	unsigned long ptp_rx_msg_pkt_reserved_type;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_announce	common.h	/^	unsigned long ptp_rx_msg_type_announce;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_delay_req	common.h	/^	unsigned long ptp_rx_msg_type_delay_req;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_delay_resp	common.h	/^	unsigned long ptp_rx_msg_type_delay_resp;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_follow_up	common.h	/^	unsigned long ptp_rx_msg_type_follow_up;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_management	common.h	/^	unsigned long ptp_rx_msg_type_management;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_pdelay_follow_up	common.h	/^	unsigned long ptp_rx_msg_type_pdelay_follow_up;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_pdelay_req	common.h	/^	unsigned long ptp_rx_msg_type_pdelay_req;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_pdelay_resp	common.h	/^	unsigned long ptp_rx_msg_type_pdelay_resp;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_rx_msg_type_sync	common.h	/^	unsigned long ptp_rx_msg_type_sync;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptp_ver	common.h	/^	unsigned long ptp_ver;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
ptpaddr	stmmac.h	/^	void __iomem *ptpaddr;$/;"	m	struct:stmmac_priv	typeref:typename:void __iomem *
px30_ops	dwmac-rk.c	/^static const struct rk_gmac_ops px30_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
px30_set_rmii_speed	dwmac-rk.c	/^static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
px30_set_to_rmii	dwmac-rk.c	/^static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
qcom_ethqos	dwmac-qcom-ethqos.c	/^struct qcom_ethqos {$/;"	s	file:
qcom_ethqos_driver	dwmac-qcom-ethqos.c	/^static struct platform_driver qcom_ethqos_driver = {$/;"	v	typeref:struct:platform_driver	file:
qcom_ethqos_match	dwmac-qcom-ethqos.c	/^static const struct of_device_id qcom_ethqos_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
qcom_ethqos_probe	dwmac-qcom-ethqos.c	/^static int qcom_ethqos_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
qcom_ethqos_remove	dwmac-qcom-ethqos.c	/^static int qcom_ethqos_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
qmode	hwif.h	/^	void (*qmode)(void __iomem *ioaddr, u32 channel, u8 qmode);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 channel,u8 qmode)
qsgmii_csr	dwmac-ipq806x.c	/^	struct regmap *qsgmii_csr;$/;"	m	struct:ipq806x_gmac	typeref:struct:regmap *	file:
quadruple_ratio	dwmac1000.h	/^	quadruple_ratio = 0x0000c000,	\/* 4:1 *\/$/;"	e	enum:rx_tx_priority_ratio
quark_default_data	dwmac-intel.c	/^static int quark_default_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
quark_info	dwmac-intel.c	/^static const struct stmmac_pci_info quark_info = {$/;"	v	typeref:typename:const struct stmmac_pci_info	file:
quark_pci_dmi	dwmac-intel.c	/^static const struct dmi_system_id quark_pci_dmi[] = {$/;"	v	typeref:typename:const struct dmi_system_id[]	file:
queue_index	stmmac.h	/^	u32 queue_index;$/;"	m	struct:stmmac_rx_queue	typeref:typename:u32
queue_index	stmmac.h	/^	u32 queue_index;$/;"	m	struct:stmmac_tx_queue	typeref:typename:u32
queue_mapping	stmmac_selftests.c	/^	u16 queue_mapping;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u16	file:
quirks	hwif.c	/^	int (*quirks)(struct stmmac_priv *priv);$/;"	m	struct:stmmac_hwif_entry	typeref:typename:int (*)(struct stmmac_priv * priv)	file:
read	hwif.h	/^	void (*read)(void __iomem *ioaddr, struct stmmac_counters *mmc);$/;"	m	struct:stmmac_mmc_ops	typeref:typename:void (*)(void __iomem * ioaddr,struct stmmac_counters * mmc)
refill_desc3	chain_mode.c	/^static void refill_desc3(void *priv_ptr, struct dma_desc *p)$/;"	f	typeref:typename:void	file:
refill_desc3	hwif.h	/^	void (*refill_desc3) (void *priv, struct dma_desc *p);$/;"	m	struct:stmmac_mode_ops	typeref:typename:void (*)(void * priv,struct dma_desc * p)
refill_desc3	ring_mode.c	/^static void refill_desc3(void *priv_ptr, struct dma_desc *p)$/;"	f	typeref:typename:void	file:
reg	dwmac-meson.c	/^	void __iomem	*reg;$/;"	m	struct:meson_dwmac	typeref:typename:void __iomem *	file:
reg_mask	common.h	/^	u32 reg_mask;$/;"	m	struct:stmmac_rx_routing	typeref:typename:u32
reg_mask	common.h	/^	unsigned int reg_mask;		\/* MII reg mask *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
reg_offset	dwmac-socfpga.c	/^	u32	reg_offset;$/;"	m	struct:socfpga_dwmac	typeref:typename:u32	file:
reg_shift	common.h	/^	u32 reg_shift;$/;"	m	struct:stmmac_rx_routing	typeref:typename:u32
reg_shift	common.h	/^	unsigned int reg_shift;		\/* MII reg shift *\/$/;"	m	struct:mii_regs	typeref:typename:unsigned int
reg_shift	dwmac-socfpga.c	/^	u32	reg_shift;$/;"	m	struct:socfpga_dwmac	typeref:typename:u32	file:
regmap	dwmac-oxnas.c	/^	struct regmap	*regmap;$/;"	m	struct:oxnas_dwmac	typeref:struct:regmap *	file:
regmap	dwmac-sti.c	/^	struct regmap *regmap;$/;"	m	struct:sti_dwmac	typeref:struct:regmap *	file:
regmap	dwmac-stm32.c	/^	struct regmap *regmap;$/;"	m	struct:stm32_dwmac	typeref:struct:regmap *	file:
regmap_field	dwmac-sun8i.c	/^	struct regmap_field *regmap_field;$/;"	m	struct:sunxi_priv_data	typeref:struct:regmap_field *	file:
regs	dwmac-dwc-qos-eth.c	/^	void __iomem *regs;$/;"	m	struct:tegra_eqos	typeref:typename:void __iomem *	file:
regs	dwmac-meson8b.c	/^	void __iomem			*regs;$/;"	m	struct:meson8b_dwmac	typeref:typename:void __iomem *	file:
regs	hwif.c	/^	const struct stmmac_regs_off regs;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const struct stmmac_regs_off	file:
regulator	dwmac-rk.c	/^	struct regulator *regulator;$/;"	m	struct:rk_priv_data	typeref:struct:regulator *	file:
regulator	dwmac-sun8i.c	/^	struct regulator *regulator;$/;"	m	struct:sunxi_priv_data	typeref:struct:regulator *	file:
regulator	dwmac-sunxi.c	/^	struct regulator *regulator;$/;"	m	struct:sunxi_priv_data	typeref:struct:regulator *	file:
release_tx_desc	hwif.h	/^	void (*release_tx_desc)(struct dma_desc *p, int mode);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int mode)
remove	dwmac-dwc-qos-eth.c	/^	int (*remove)(struct platform_device *pdev);$/;"	m	struct:dwc_eth_dwmac_data	typeref:typename:int (*)(struct platform_device * pdev)	file:
remove_sa	stmmac_selftests.c	/^	int remove_sa;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
res1	stmmac.h	/^		u8 res1:4;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8:4
res2	stmmac.h	/^		u32 res2;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u32
reset	dwmac-dwc-qos-eth.c	/^	struct gpio_desc *reset;$/;"	m	struct:tegra_eqos	typeref:struct:gpio_desc *	file:
reset	hwif.h	/^	int (*reset)(void __iomem *ioaddr);$/;"	m	struct:stmmac_dma_ops	typeref:typename:int (*)(void __iomem * ioaddr)
reset_eee_mode	hwif.h	/^	void (*reset_eee_mode)(struct mac_device_info *hw);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw)
restore_hw_vlan_rx_fltr	hwif.h	/^	void (*restore_hw_vlan_rx_fltr)(struct net_device *dev,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct net_device * dev,struct mac_device_info * hw)
resume	dwmac-stm32.c	/^	void (*resume)(struct stm32_dwmac *dwmac);$/;"	m	struct:stm32_ops	typeref:typename:void (*)(struct stm32_dwmac * dwmac)	file:
rf	stmmac.h	/^		u8 rf:1;$/;"	m	struct:stmmac_tc_entry::__anon84d70a400208	typeref:typename:u8:1
rfa	dwmac1000.h	/^enum rfa {$/;"	g
rfd	dwmac1000.h	/^enum rfd {$/;"	g
rgmii_adv	common.h	/^struct rgmii_adv {$/;"	s
rgmii_base	dwmac-qcom-ethqos.c	/^	void __iomem *rgmii_base;$/;"	m	struct:qcom_ethqos	typeref:typename:void __iomem *	file:
rgmii_clk	dwmac-qcom-ethqos.c	/^	struct clk *rgmii_clk;$/;"	m	struct:qcom_ethqos	typeref:struct:clk *	file:
rgmii_clk_rate	dwmac-qcom-ethqos.c	/^	unsigned int rgmii_clk_rate;$/;"	m	struct:qcom_ethqos	typeref:typename:unsigned int	file:
rgmii_dump	dwmac-qcom-ethqos.c	/^static void rgmii_dump(struct qcom_ethqos *ethqos)$/;"	f	typeref:typename:void	file:
rgmii_readl	dwmac-qcom-ethqos.c	/^static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)$/;"	f	typeref:typename:int	file:
rgmii_tx_clk	dwmac-meson8b.c	/^	struct clk			*rgmii_tx_clk;$/;"	m	struct:meson8b_dwmac	typeref:struct:clk *	file:
rgmii_tx_en	dwmac-meson8b.c	/^	struct clk_gate		rgmii_tx_en;$/;"	m	struct:meson8b_dwmac_clk_configs	typeref:struct:clk_gate	file:
rgmii_updatel	dwmac-qcom-ethqos.c	/^static void rgmii_updatel(struct qcom_ethqos *ethqos,$/;"	f	typeref:typename:void	file:
rgmii_writel	dwmac-qcom-ethqos.c	/^static void rgmii_writel(struct qcom_ethqos *ethqos,$/;"	f	typeref:typename:void	file:
ring_mode_ops	ring_mode.c	/^const struct stmmac_mode_ops ring_mode_ops = {$/;"	v	typeref:typename:const struct stmmac_mode_ops
rk3128_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3128_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3128_set_rgmii_speed	dwmac-rk.c	/^static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3128_set_rmii_speed	dwmac-rk.c	/^static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3128_set_to_rgmii	dwmac-rk.c	/^static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3128_set_to_rmii	dwmac-rk.c	/^static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3228_integrated_phy_powerup	dwmac-rk.c	/^static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)$/;"	f	typeref:typename:void	file:
rk3228_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3228_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3228_set_rgmii_speed	dwmac-rk.c	/^static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3228_set_rmii_speed	dwmac-rk.c	/^static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3228_set_to_rgmii	dwmac-rk.c	/^static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3228_set_to_rmii	dwmac-rk.c	/^static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3288_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3288_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3288_set_rgmii_speed	dwmac-rk.c	/^static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3288_set_rmii_speed	dwmac-rk.c	/^static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3288_set_to_rgmii	dwmac-rk.c	/^static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3288_set_to_rmii	dwmac-rk.c	/^static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3328_integrated_phy_powerup	dwmac-rk.c	/^static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)$/;"	f	typeref:typename:void	file:
rk3328_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3328_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3328_set_rgmii_speed	dwmac-rk.c	/^static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3328_set_rmii_speed	dwmac-rk.c	/^static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3328_set_to_rgmii	dwmac-rk.c	/^static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3328_set_to_rmii	dwmac-rk.c	/^static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3366_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3366_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3366_set_rgmii_speed	dwmac-rk.c	/^static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3366_set_rmii_speed	dwmac-rk.c	/^static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3366_set_to_rgmii	dwmac-rk.c	/^static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3366_set_to_rmii	dwmac-rk.c	/^static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3368_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3368_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3368_set_rgmii_speed	dwmac-rk.c	/^static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3368_set_rmii_speed	dwmac-rk.c	/^static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3368_set_to_rgmii	dwmac-rk.c	/^static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3368_set_to_rmii	dwmac-rk.c	/^static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk3399_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rk3399_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rk3399_set_rgmii_speed	dwmac-rk.c	/^static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3399_set_rmii_speed	dwmac-rk.c	/^static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rk3399_set_to_rgmii	dwmac-rk.c	/^static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,$/;"	f	typeref:typename:void	file:
rk3399_set_to_rmii	dwmac-rk.c	/^static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rk_fix_speed	dwmac-rk.c	/^static void rk_fix_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
rk_gmac_clk_init	dwmac-rk.c	/^static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)$/;"	f	typeref:typename:int	file:
rk_gmac_dwmac_driver	dwmac-rk.c	/^static struct platform_driver rk_gmac_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
rk_gmac_dwmac_match	dwmac-rk.c	/^static const struct of_device_id rk_gmac_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
rk_gmac_integrated_phy_powerdown	dwmac-rk.c	/^static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)$/;"	f	typeref:typename:void	file:
rk_gmac_integrated_phy_powerup	dwmac-rk.c	/^static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)$/;"	f	typeref:typename:void	file:
rk_gmac_ops	dwmac-rk.c	/^struct rk_gmac_ops {$/;"	s	file:
rk_gmac_powerdown	dwmac-rk.c	/^static void rk_gmac_powerdown(struct rk_priv_data *gmac)$/;"	f	typeref:typename:void	file:
rk_gmac_powerup	dwmac-rk.c	/^static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:int	file:
rk_gmac_probe	dwmac-rk.c	/^static int rk_gmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
rk_gmac_remove	dwmac-rk.c	/^static int rk_gmac_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
rk_gmac_resume	dwmac-rk.c	/^static int rk_gmac_resume(struct device *dev)$/;"	f	typeref:typename:int	file:
rk_gmac_setup	dwmac-rk.c	/^static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,$/;"	f	typeref:struct:rk_priv_data *	file:
rk_gmac_suspend	dwmac-rk.c	/^static int rk_gmac_suspend(struct device *dev)$/;"	f	typeref:typename:int	file:
rk_priv_data	dwmac-rk.c	/^struct rk_priv_data {$/;"	s	file:
rmii_clk_from_mac	dwmac-mediatek.c	/^	bool rmii_clk_from_mac;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:typename:bool	file:
rmii_refclk_ext	dwmac-imx.c	/^	bool rmii_refclk_ext;$/;"	m	struct:imx_priv_data	typeref:typename:bool	file:
rmii_rxc	dwmac-mediatek.c	/^	bool rmii_rxc;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:typename:bool	file:
rmon	common.h	/^	unsigned int rmon;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rss	stmmac.h	/^	struct stmmac_rss rss;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_rss
rss_configure	hwif.h	/^	int (*rss_configure)(struct mac_device_info *hw,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw,struct stmmac_rss * cfg,u32 num_rxq)
rssen	common.h	/^	unsigned int rssen;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rst	dwmac-dwc-qos-eth.c	/^	struct reset_control *rst;$/;"	m	struct:tegra_eqos	typeref:struct:reset_control *	file:
rst_ephy	dwmac-sun8i.c	/^	struct reset_control *rst_ephy;$/;"	m	struct:sunxi_priv_data	typeref:struct:reset_control *	file:
rtc_control	dwmac1000.h	/^enum rtc_control {$/;"	g
rv1108_ops	dwmac-rk.c	/^static const struct rk_gmac_ops rv1108_ops = {$/;"	v	typeref:typename:const struct rk_gmac_ops	file:
rv1108_set_rmii_speed	dwmac-rk.c	/^static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)$/;"	f	typeref:typename:void	file:
rv1108_set_to_rmii	dwmac-rk.c	/^static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)$/;"	f	typeref:typename:void	file:
rx_buf_unav_irq	common.h	/^	unsigned long rx_buf_unav_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_coal_frames	stmmac.h	/^	u32 rx_coal_frames;$/;"	m	struct:stmmac_priv	typeref:typename:u32
rx_coe	common.h	/^	unsigned int rx_coe;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rx_coe_type1	common.h	/^	unsigned int rx_coe_type1;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rx_coe_type2	common.h	/^	unsigned int rx_coe_type2;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rx_collision	common.h	/^	unsigned long rx_collision;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_copybreak	stmmac.h	/^	unsigned int rx_copybreak;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
rx_count_frames	stmmac.h	/^	u32 rx_count_frames;$/;"	m	struct:stmmac_rx_queue	typeref:typename:u32
rx_crc_errors	common.h	/^	unsigned long rx_crc_errors;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_csum	common.h	/^	unsigned int rx_csum;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
rx_delay	dwmac-mediatek.c	/^	u32 rx_delay;$/;"	m	struct:mac_delay_struct	typeref:typename:u32	file:
rx_delay	dwmac-rk.c	/^	int rx_delay;$/;"	m	struct:rk_priv_data	typeref:typename:int	file:
rx_delay_max	dwmac-mediatek.c	/^	u32 rx_delay_max;$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:u32	file:
rx_delay_max	dwmac-sun8i.c	/^	u8 rx_delay_max;$/;"	m	struct:emac_variant	typeref:typename:u8	file:
rx_delay_ns	dwmac-meson8b.c	/^	u32				rx_delay_ns;$/;"	m	struct:meson8b_dwmac	typeref:typename:u32	file:
rx_desc	common.h	/^	unsigned long rx_desc;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_early_irq	common.h	/^	unsigned long rx_early_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_extended_status	hwif.h	/^	void (*rx_extended_status)(void *data, struct stmmac_extra_stats *x,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(void * data,struct stmmac_extra_stats * x,struct dma_extended_desc * p)
rx_fifo_size	common.h	/^	unsigned int rx_fifo_size;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rx_frame_status	common.h	/^enum rx_frame_status {$/;"	g
rx_gmac_overflow	common.h	/^	unsigned long rx_gmac_overflow;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_inv	dwmac-mediatek.c	/^	bool rx_inv;$/;"	m	struct:mac_delay_struct	typeref:typename:bool	file:
rx_ipc	hwif.h	/^	int (*rx_ipc)(struct mac_device_info *hw);$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct mac_device_info * hw)
rx_length	common.h	/^	unsigned long rx_length;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_mii	common.h	/^	unsigned long rx_mii;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_missed_cntr	common.h	/^	unsigned long rx_missed_cntr;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_multicast	common.h	/^	unsigned long rx_multicast;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_normal_irq_n	common.h	/^	unsigned long rx_normal_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_not_ls	common.h	/^	rx_not_ls = 0x10,$/;"	e	enum:rx_frame_status
rx_overflow_cntr	common.h	/^	unsigned long rx_overflow_cntr;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_overflow_irq	common.h	/^	unsigned long rx_overflow_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_pkt_n	common.h	/^	unsigned long rx_pkt_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_process_stopped_irq	common.h	/^	unsigned long rx_process_stopped_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_queue	stmmac.h	/^	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_rx_queue[]
rx_queue_enable	hwif.h	/^	void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u8 mode,u32 queue)
rx_queue_prio	hwif.h	/^	void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 prio,u32 queue)
rx_queue_routing	hwif.h	/^	void (*rx_queue_routing)(struct mac_device_info *hw, u8 packet,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u8 packet,u32 queue)
rx_riwt	stmmac.h	/^	u32 rx_riwt;$/;"	m	struct:stmmac_priv	typeref:typename:u32
rx_split_hdr_pkt_n	common.h	/^	unsigned long rx_split_hdr_pkt_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_status	hwif.h	/^	int (*rx_status)(void *data, struct stmmac_extra_stats *x,$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(void * data,struct stmmac_extra_stats * x,struct dma_desc * p)
rx_tail_addr	stmmac.h	/^	u32 rx_tail_addr;$/;"	m	struct:stmmac_rx_queue	typeref:typename:u32
rx_tx_priority_ratio	dwmac1000.h	/^enum rx_tx_priority_ratio {$/;"	g
rx_vlan	common.h	/^	unsigned long rx_vlan;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_watchdog	common.h	/^	unsigned long rx_watchdog;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_watchdog	hwif.h	/^	void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt, u32 number_chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 riwt,u32 number_chan)
rx_watchdog_irq	common.h	/^	unsigned long rx_watchdog_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
rx_zeroc_thresh	stmmac.h	/^	u32 rx_zeroc_thresh;$/;"	m	struct:stmmac_rx_queue	typeref:typename:u32
rxfifo_over_2048	common.h	/^	unsigned int rxfifo_over_2048;$/;"	m	struct:dma_features	typeref:typename:unsigned int
rxp_config	hwif.h	/^	int (*rxp_config)(void __iomem *ioaddr, struct stmmac_tc_entry *entries,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(void __iomem * ioaddr,struct stmmac_tc_entry * entries,unsigned int count)
sa_filter_fail	common.h	/^	unsigned long sa_filter_fail;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
sa_rx_filter_fail	common.h	/^	unsigned long sa_rx_filter_fail;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
safety_feat_config	hwif.h	/^	int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(void __iomem * ioaddr,unsigned int asp)
safety_feat_dump	hwif.h	/^	int (*safety_feat_dump)(struct stmmac_safety_stats *stats,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct stmmac_safety_stats * stats,int index,unsigned long * count,const char ** desc)
safety_feat_irq_status	hwif.h	/^	int (*safety_feat_irq_status)(struct net_device *ndev,$/;"	m	struct:stmmac_ops	typeref:typename:int (*)(struct net_device * ndev,void __iomem * ioaddr,unsigned int asp,struct stmmac_safety_stats * stats)
sarc	stmmac_selftests.c	/^	int sarc;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
sarc_configure	hwif.h	/^	void (*sarc_configure)(void __iomem *ioaddr, int val);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,int val)
sarc_type	stmmac.h	/^	u32 sarc_type;$/;"	m	struct:stmmac_priv	typeref:typename:u32
sec_addr	stmmac.h	/^	dma_addr_t sec_addr;$/;"	m	struct:stmmac_rx_buffer	typeref:typename:dma_addr_t
sec_page	stmmac.h	/^	struct page *sec_page;$/;"	m	struct:stmmac_rx_buffer	typeref:struct:page *
serdes_status_poll	dwmac-intel.c	/^static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,$/;"	f	typeref:typename:int	file:
service_task	stmmac.h	/^	struct work_struct service_task;$/;"	m	struct:stmmac_priv	typeref:struct:work_struct
set_16kib_bfsize	dwmac4_descs.c	/^static int set_16kib_bfsize(int mtu)$/;"	f	typeref:typename:int	file:
set_16kib_bfsize	hwif.h	/^	int (*set_16kib_bfsize)(int mtu);$/;"	m	struct:stmmac_mode_ops	typeref:typename:int (*)(int mtu)
set_16kib_bfsize	ring_mode.c	/^static int set_16kib_bfsize(int mtu)$/;"	f	typeref:typename:int	file:
set_addr	hwif.h	/^	void (*set_addr)(struct dma_desc *p, dma_addr_t addr);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,dma_addr_t addr)
set_arp_offload	hwif.h	/^	void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,bool en,u32 addr)
set_bfsize	hwif.h	/^	void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,int bfsize,u32 chan)
set_eee_mode	hwif.h	/^	void (*set_eee_mode)(struct mac_device_info *hw,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,bool en_tx_lpi_clockgating)
set_eee_pls	hwif.h	/^	void (*set_eee_pls)(struct mac_device_info *hw, int link);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,int link)
set_eee_timer	hwif.h	/^	void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,int ls,int tw)
set_filter	hwif.h	/^	void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,struct net_device * dev)
set_intf_mode	dwmac-imx.c	/^	int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);$/;"	m	struct:imx_dwmac_ops	typeref:typename:int (*)(struct plat_stmmacenet_data * plat_dat)	file:
set_mac	hwif.h	/^	void (*set_mac)(void __iomem *ioaddr, bool enable);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool enable)
set_mac_loopback	hwif.h	/^	void (*set_mac_loopback)(void __iomem *ioaddr, bool enable);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(void __iomem * ioaddr,bool enable)
set_mode	dwmac-stm32.c	/^	int (*set_mode)(struct plat_stmmacenet_data *plat_dat);$/;"	m	struct:stm32_ops	typeref:typename:int (*)(struct plat_stmmacenet_data * plat_dat)	file:
set_mss	hwif.h	/^	void (*set_mss)(struct dma_desc *p, unsigned int mss);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,unsigned int mss)
set_mtl_tx_queue_weight	hwif.h	/^	void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 weight,u32 queue)
set_phy_mode	dwmac-meson8b.c	/^	int (*set_phy_mode)(struct meson8b_dwmac *dwmac);$/;"	m	struct:meson8b_dwmac_data	typeref:typename:int (*)(struct meson8b_dwmac * dwmac)	file:
set_phy_mode	dwmac-socfpga.c	/^	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);$/;"	m	struct:socfpga_dwmac_ops	typeref:typename:int (*)(struct socfpga_dwmac * dwmac_priv)	file:
set_rgmii_speed	dwmac-rk.c	/^	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);$/;"	m	struct:rk_gmac_ops	typeref:typename:void (*)(struct rk_priv_data * bsp_priv,int speed)	file:
set_rmii_speed	dwmac-rk.c	/^	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);$/;"	m	struct:rk_gmac_ops	typeref:typename:void (*)(struct rk_priv_data * bsp_priv,int speed)	file:
set_rx_owner	hwif.h	/^	void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,int disable_rx_ic)
set_rx_ring_len	hwif.h	/^	void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 len,u32 chan)
set_rx_tail_ptr	hwif.h	/^	void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 tail_ptr,u32 chan)
set_sarc	hwif.h	/^	void (*set_sarc)(struct dma_desc *p, u32 sarc_type);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,u32 sarc_type)
set_sec_addr	hwif.h	/^	void (*set_sec_addr)(struct dma_desc *p, dma_addr_t addr, bool buf2_valid);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,dma_addr_t addr,bool buf2_valid)
set_tbs	hwif.h	/^	void (*set_tbs)(struct dma_edesc *p, u32 sec, u32 nsec);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_edesc * p,u32 sec,u32 nsec)
set_to_rgmii	dwmac-rk.c	/^	void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,$/;"	m	struct:rk_gmac_ops	typeref:typename:void (*)(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)	file:
set_to_rmii	dwmac-rk.c	/^	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);$/;"	m	struct:rk_gmac_ops	typeref:typename:void (*)(struct rk_priv_data * bsp_priv)	file:
set_tx_ic	hwif.h	/^	void (*set_tx_ic)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p)
set_tx_owner	hwif.h	/^	void (*set_tx_owner)(struct dma_desc *p);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p)
set_tx_ring_len	hwif.h	/^	void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 len,u32 chan)
set_tx_tail_ptr	hwif.h	/^	void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 tail_ptr,u32 chan)
set_umac_addr	hwif.h	/^	void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)
set_vlan	hwif.h	/^	void (*set_vlan)(struct dma_desc *p, u32 type);$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,u32 type)
set_vlan_tag	hwif.h	/^	void (*set_vlan_tag)(struct dma_desc *p, u16 tag, u16 inner_tag,$/;"	m	struct:stmmac_desc_ops	typeref:typename:void (*)(struct dma_desc * p,u16 tag,u16 inner_tag,u32 inner_type)
setup	dwmac-intel.c	/^	int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);$/;"	m	struct:stmmac_pci_info	typeref:typename:int (*)(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)	file:
setup	hwif.c	/^	int (*setup)(struct stmmac_priv *priv);$/;"	m	struct:stmmac_hwif_entry	typeref:typename:int (*)(struct stmmac_priv * priv)	file:
setup	stmmac_pci.c	/^	int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);$/;"	m	struct:stmmac_pci_info	typeref:typename:int (*)(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)	file:
setup_cbs	hwif.h	/^	int (*setup_cbs)(struct stmmac_priv *priv,$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv,struct tc_cbs_qopt_offload * qopt)
setup_cls	hwif.h	/^	int (*setup_cls)(struct stmmac_priv *priv,$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv,struct flow_cls_offload * cls)
setup_cls_u32	hwif.h	/^	int (*setup_cls_u32)(struct stmmac_priv *priv,$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv,struct tc_cls_u32_offload * cls)
setup_etf	hwif.h	/^	int (*setup_etf)(struct stmmac_priv *priv,$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv,struct tc_etf_qopt_offload * qopt)
setup_taprio	hwif.h	/^	int (*setup_taprio)(struct stmmac_priv *priv,$/;"	m	struct:stmmac_tc_ops	typeref:typename:int (*)(struct stmmac_priv * priv,struct tc_taprio_qopt_offload * qopt)
sgmii_adapter_base	altr_tse_pcs.h	/^	void __iomem *sgmii_adapter_base;$/;"	m	struct:tse_pcs	typeref:typename:void __iomem *
show_rx_process_state	dwmac_lib.c	/^static void show_rx_process_state(unsigned int status)$/;"	f	typeref:typename:void	file:
show_tx_process_state	dwmac_lib.c	/^static void show_tx_process_state(unsigned int status)$/;"	f	typeref:typename:void	file:
size	stmmac_selftests.c	/^	int size;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
sizeof_stat	stmmac_ethtool.c	/^	int sizeof_stat;$/;"	m	struct:stmmac_stats	typeref:typename:int	file:
skb	stmmac.h	/^		struct sk_buff *skb;$/;"	m	struct:stmmac_rx_queue::__anon84d70a400108	typeref:struct:sk_buff *
sma_mdio	common.h	/^	unsigned int sma_mdio;$/;"	m	struct:dma_features	typeref:typename:unsigned int
snps_gmac5_default_data	stmmac_pci.c	/^static int snps_gmac5_default_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
snps_gmac5_pci_info	stmmac_pci.c	/^static const struct stmmac_pci_info snps_gmac5_pci_info = {$/;"	v	typeref:typename:const struct stmmac_pci_info	file:
soc_has_internal_phy	dwmac-sun8i.c	/^	bool soc_has_internal_phy;$/;"	m	struct:emac_variant	typeref:typename:bool	file:
socfpga_dwmac	dwmac-socfpga.c	/^struct socfpga_dwmac {$/;"	s	file:
socfpga_dwmac_driver	dwmac-socfpga.c	/^static struct platform_driver socfpga_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
socfpga_dwmac_fix_mac_speed	dwmac-socfpga.c	/^static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
socfpga_dwmac_match	dwmac-socfpga.c	/^static const struct of_device_id socfpga_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
socfpga_dwmac_ops	dwmac-socfpga.c	/^struct socfpga_dwmac_ops {$/;"	s	file:
socfpga_dwmac_parse_data	dwmac-socfpga.c	/^static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)$/;"	f	typeref:typename:int	file:
socfpga_dwmac_pm_ops	dwmac-socfpga.c	/^static const struct dev_pm_ops socfpga_dwmac_pm_ops = {$/;"	v	typeref:typename:const struct dev_pm_ops	file:
socfpga_dwmac_probe	dwmac-socfpga.c	/^static int socfpga_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
socfpga_dwmac_resume	dwmac-socfpga.c	/^static int socfpga_dwmac_resume(struct device *dev)$/;"	f	typeref:typename:int	file:
socfpga_dwmac_runtime_resume	dwmac-socfpga.c	/^static int __maybe_unused socfpga_dwmac_runtime_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
socfpga_dwmac_runtime_suspend	dwmac-socfpga.c	/^static int __maybe_unused socfpga_dwmac_runtime_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
socfpga_gen10_ops	dwmac-socfpga.c	/^static const struct socfpga_dwmac_ops socfpga_gen10_ops = {$/;"	v	typeref:typename:const struct socfpga_dwmac_ops	file:
socfpga_gen10_set_phy_mode	dwmac-socfpga.c	/^static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
socfpga_gen5_ops	dwmac-socfpga.c	/^static const struct socfpga_dwmac_ops socfpga_gen5_ops = {$/;"	v	typeref:typename:const struct socfpga_dwmac_ops	file:
socfpga_gen5_set_phy_mode	dwmac-socfpga.c	/^static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
socfpga_get_plat_phymode	dwmac-socfpga.c	/^static int socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
socfpga_set_phy_mode_common	dwmac-socfpga.c	/^static int socfpga_set_phy_mode_common(int phymode, u32 *val)$/;"	f	typeref:typename:int	file:
speed	dwmac-qcom-ethqos.c	/^	unsigned int speed;$/;"	m	struct:qcom_ethqos	typeref:typename:unsigned int	file:
speed	dwmac-sti.c	/^	u32 speed;$/;"	m	struct:sti_dwmac	typeref:typename:u32	file:
speed	dwmac-stm32.c	/^	u32 speed;$/;"	m	struct:stm32_dwmac	typeref:typename:u32	file:
speed	stmmac.h	/^	int speed;$/;"	m	struct:stmmac_priv	typeref:typename:int
speed10	common.h	/^	u32 speed10;$/;"	m	struct:mac_link	typeref:typename:u32
speed100	common.h	/^	u32 speed100;$/;"	m	struct:mac_link	typeref:typename:u32
speed1000	common.h	/^	u32 speed1000;$/;"	m	struct:mac_link	typeref:typename:u32
speed10000	common.h	/^		u32 speed10000;$/;"	m	struct:mac_link::__anon3fde68840108	typeref:typename:u32
speed100000	common.h	/^		u32 speed100000;$/;"	m	struct:mac_link::__anon3fde68840208	typeref:typename:u32
speed2500	common.h	/^		u32 speed2500;$/;"	m	struct:mac_link::__anon3fde68840108	typeref:typename:u32
speed2500	common.h	/^	u32 speed2500;$/;"	m	struct:mac_link	typeref:typename:u32
speed25000	common.h	/^		u32 speed25000;$/;"	m	struct:mac_link::__anon3fde68840208	typeref:typename:u32
speed40000	common.h	/^		u32 speed40000;$/;"	m	struct:mac_link::__anon3fde68840208	typeref:typename:u32
speed5000	common.h	/^		u32 speed5000;$/;"	m	struct:mac_link::__anon3fde68840108	typeref:typename:u32
speed50000	common.h	/^		u32 speed50000;$/;"	m	struct:mac_link::__anon3fde68840208	typeref:typename:u32
speed_mask	common.h	/^	u32 speed_mask;$/;"	m	struct:mac_link	typeref:typename:u32
sph	stmmac.h	/^	int sph;$/;"	m	struct:stmmac_priv	typeref:typename:int
sphen	common.h	/^	unsigned int sphen;$/;"	m	struct:dma_features	typeref:typename:unsigned int
splitter_base	dwmac-socfpga.c	/^	void __iomem *splitter_base;$/;"	m	struct:socfpga_dwmac	typeref:typename:void __iomem *	file:
sport	stmmac_selftests.c	/^	int sport;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
src	stmmac_selftests.c	/^	unsigned char *src;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:unsigned char *	file:
sstats	stmmac.h	/^	struct stmmac_safety_stats sstats;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_safety_stats
start	stmmac.h	/^	struct timespec64 start;$/;"	m	struct:stmmac_pps_cfg	typeref:struct:timespec64
start_rx	hwif.h	/^	void (*start_rx)(void __iomem *ioaddr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan)
start_tx	hwif.h	/^	void (*start_tx)(void __iomem *ioaddr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan)
stat_offset	stmmac_ethtool.c	/^	int stat_offset;$/;"	m	struct:stmmac_stats	typeref:typename:int	file:
stat_string	stmmac_ethtool.c	/^	char stat_string[ETH_GSTRING_LEN];$/;"	m	struct:stmmac_stats	typeref:typename:char[]	file:
state	stmmac.h	/^	unsigned long state;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned long
state	stmmac.h	/^	} state;$/;"	m	struct:stmmac_rx_queue	typeref:struct:stmmac_rx_queue::__anon84d70a400108
state_saved	stmmac.h	/^	unsigned int state_saved;$/;"	m	struct:stmmac_rx_queue	typeref:typename:unsigned int
sti_dwmac	dwmac-sti.c	/^struct sti_dwmac {$/;"	s	file:
sti_dwmac_driver	dwmac-sti.c	/^static struct platform_driver sti_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
sti_dwmac_match	dwmac-sti.c	/^static const struct of_device_id sti_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
sti_dwmac_of_data	dwmac-sti.c	/^struct sti_dwmac_of_data {$/;"	s	file:
sti_dwmac_parse_data	dwmac-sti.c	/^static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,$/;"	f	typeref:typename:int	file:
sti_dwmac_probe	dwmac-sti.c	/^static int sti_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
sti_dwmac_remove	dwmac-sti.c	/^static int sti_dwmac_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
sti_dwmac_resume	dwmac-sti.c	/^static int sti_dwmac_resume(struct device *dev)$/;"	f	typeref:typename:int	file:
sti_dwmac_set_mode	dwmac-sti.c	/^static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
sti_dwmac_suspend	dwmac-sti.c	/^static int sti_dwmac_suspend(struct device *dev)$/;"	f	typeref:typename:int	file:
stid127_dwmac_data	dwmac-sti.c	/^static const struct sti_dwmac_of_data stid127_dwmac_data = {$/;"	v	typeref:typename:const struct sti_dwmac_of_data	file:
stid127_fix_retime_src	dwmac-sti.c	/^static void stid127_fix_retime_src(void *priv, u32 spd)$/;"	f	typeref:typename:void	file:
stih4xx_dwmac_data	dwmac-sti.c	/^static const struct sti_dwmac_of_data stih4xx_dwmac_data = {$/;"	v	typeref:typename:const struct sti_dwmac_of_data	file:
stih4xx_fix_retime_src	dwmac-sti.c	/^static void stih4xx_fix_retime_src(void *priv, u32 spd)$/;"	f	typeref:typename:void	file:
stih4xx_tx_retime_val	dwmac-sti.c	/^static u32 stih4xx_tx_retime_val[] = {$/;"	v	typeref:typename:u32[]	file:
stm32_dwmac	dwmac-stm32.c	/^struct stm32_dwmac {$/;"	s	file:
stm32_dwmac_clk_disable	dwmac-stm32.c	/^static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)$/;"	f	typeref:typename:void	file:
stm32_dwmac_driver	dwmac-stm32.c	/^static struct platform_driver stm32_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
stm32_dwmac_init	dwmac-stm32.c	/^static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)$/;"	f	typeref:typename:int	file:
stm32_dwmac_match	dwmac-stm32.c	/^static const struct of_device_id stm32_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
stm32_dwmac_parse_data	dwmac-stm32.c	/^static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,$/;"	f	typeref:typename:int	file:
stm32_dwmac_probe	dwmac-stm32.c	/^static int stm32_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
stm32_dwmac_remove	dwmac-stm32.c	/^static int stm32_dwmac_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
stm32_dwmac_resume	dwmac-stm32.c	/^static int stm32_dwmac_resume(struct device *dev)$/;"	f	typeref:typename:int	file:
stm32_dwmac_suspend	dwmac-stm32.c	/^static int stm32_dwmac_suspend(struct device *dev)$/;"	f	typeref:typename:int	file:
stm32_ops	dwmac-stm32.c	/^struct stm32_ops {$/;"	s	file:
stm32mcu_dwmac_data	dwmac-stm32.c	/^static struct stm32_ops stm32mcu_dwmac_data = {$/;"	v	typeref:struct:stm32_ops	file:
stm32mcu_set_mode	dwmac-stm32.c	/^static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)$/;"	f	typeref:typename:int	file:
stm32mcu_suspend	dwmac-stm32.c	/^static int stm32mcu_suspend(struct stm32_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
stm32mp1_clk_prepare	dwmac-stm32.c	/^static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)$/;"	f	typeref:typename:int	file:
stm32mp1_dwmac_data	dwmac-stm32.c	/^static struct stm32_ops stm32mp1_dwmac_data = {$/;"	v	typeref:struct:stm32_ops	file:
stm32mp1_parse_data	dwmac-stm32.c	/^static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,$/;"	f	typeref:typename:int	file:
stm32mp1_resume	dwmac-stm32.c	/^static void stm32mp1_resume(struct stm32_dwmac *dwmac)$/;"	f	typeref:typename:void	file:
stm32mp1_set_mode	dwmac-stm32.c	/^static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)$/;"	f	typeref:typename:int	file:
stm32mp1_suspend	dwmac-stm32.c	/^static int stm32mp1_suspend(struct stm32_dwmac *dwmac)$/;"	f	typeref:typename:int	file:
stmmac-objs	Makefile	/^stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\\$/;"	m
stmmac-pci-objs	Makefile	/^stmmac-pci-objs:= stmmac_pci.o$/;"	m
stmmac-platform-objs	Makefile	/^stmmac-platform-objs:= stmmac_platform.o$/;"	m
stmmac_acpi_clock_setup	stmmac_platform.c	/^int stmmac_acpi_clock_setup(struct plat_stmmacenet_data *plat,$/;"	f	typeref:typename:int
stmmac_acpi_phy	stmmac_platform.c	/^static int stmmac_acpi_phy(struct plat_stmmacenet_data *plat,$/;"	f	typeref:typename:int	file:
stmmac_add_hw_vlan_rx_fltr	hwif.h	/^#define stmmac_add_hw_vlan_rx_fltr(/;"	d
stmmac_adjust_freq	stmmac_ptp.c	/^static int stmmac_adjust_freq(struct ptp_clock_info *ptp, s32 ppb)$/;"	f	typeref:typename:int	file:
stmmac_adjust_systime	hwif.h	/^#define stmmac_adjust_systime(/;"	d
stmmac_adjust_time	stmmac_ptp.c	/^static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)$/;"	f	typeref:typename:int	file:
stmmac_axi	hwif.h	/^#define stmmac_axi(/;"	d
stmmac_axi_setup	stmmac_platform.c	/^static struct stmmac_axi *stmmac_axi_setup(struct platform_device *pdev)$/;"	f	typeref:struct:stmmac_axi *	file:
stmmac_axi_setup_acpi	stmmac_platform.c	/^static struct stmmac_axi * stmmac_axi_setup_acpi(struct platform_device *pdev)$/;"	f	typeref:struct:stmmac_axi *	file:
stmmac_bus_clks_config	stmmac_main.c	/^int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)$/;"	f	typeref:typename:int
stmmac_change_mtu	stmmac_main.c	/^static int stmmac_change_mtu(struct net_device *dev, int new_mtu)$/;"	f	typeref:typename:int	file:
stmmac_channel	stmmac.h	/^struct stmmac_channel {$/;"	s
stmmac_check_ether_addr	stmmac_main.c	/^static void stmmac_check_ether_addr(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_check_if_running	stmmac_ethtool.c	/^static int stmmac_check_if_running(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_check_pcs_mode	stmmac_main.c	/^static void stmmac_check_pcs_mode(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_clean_desc3	hwif.h	/^#define stmmac_clean_desc3(/;"	d
stmmac_clear_desc	hwif.h	/^#define stmmac_clear_desc(/;"	d
stmmac_clear_descriptors	stmmac_main.c	/^static void stmmac_clear_descriptors(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_clear_rx_descriptors	stmmac_main.c	/^static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
stmmac_clear_tx_descriptors	stmmac_main.c	/^static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
stmmac_clk_csr_set	stmmac_main.c	/^static void stmmac_clk_csr_set(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_cmdline_opt	stmmac_main.c	/^static int __init stmmac_cmdline_opt(char *str)$/;"	f	typeref:typename:int __init	file:
stmmac_config_addend	hwif.h	/^#define stmmac_config_addend(/;"	d
stmmac_config_cbs	hwif.h	/^#define stmmac_config_cbs(/;"	d
stmmac_config_hw_tstamping	hwif.h	/^#define stmmac_config_hw_tstamping(/;"	d
stmmac_config_l3_filter	hwif.h	/^#define stmmac_config_l3_filter(/;"	d
stmmac_config_l4_filter	hwif.h	/^#define stmmac_config_l4_filter(/;"	d
stmmac_config_sub_second_increment	hwif.h	/^#define stmmac_config_sub_second_increment(/;"	d
stmmac_configure_cbs	stmmac_main.c	/^static void stmmac_configure_cbs(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_core_init	hwif.h	/^#define stmmac_core_init(/;"	d
stmmac_counters	mmc.h	/^struct stmmac_counters {$/;"	s
stmmac_default_data	stmmac_pci.c	/^static int stmmac_default_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
stmmac_del_hw_vlan_rx_fltr	hwif.h	/^#define stmmac_del_hw_vlan_rx_fltr(/;"	d
stmmac_desc_ops	hwif.h	/^struct stmmac_desc_ops {$/;"	s
stmmac_device_event	stmmac_main.c	/^static int stmmac_device_event(struct notifier_block *unused,$/;"	f	typeref:typename:int	file:
stmmac_disable_all_queues	stmmac_main.c	/^static void stmmac_disable_all_queues(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_disable_dma_irq	hwif.h	/^#define stmmac_disable_dma_irq(/;"	d
stmmac_disable_eee_mode	stmmac_main.c	/^void stmmac_disable_eee_mode(struct stmmac_priv *priv)$/;"	f	typeref:typename:void
stmmac_display_ring	hwif.h	/^#define stmmac_display_ring(/;"	d
stmmac_display_rings	stmmac_main.c	/^static void stmmac_display_rings(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_display_rx_rings	stmmac_main.c	/^static void stmmac_display_rx_rings(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_display_tx_rings	stmmac_main.c	/^static void stmmac_display_tx_rings(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_dma_cap_show	stmmac_main.c	/^static int stmmac_dma_cap_show(struct seq_file *seq, void *v)$/;"	f	typeref:typename:int	file:
stmmac_dma_diagnostic_fr	hwif.h	/^#define stmmac_dma_diagnostic_fr(/;"	d
stmmac_dma_init	hwif.h	/^#define stmmac_dma_init(/;"	d
stmmac_dma_interrupt	stmmac_main.c	/^static void stmmac_dma_interrupt(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_dma_interrupt_status	hwif.h	/^#define stmmac_dma_interrupt_status(/;"	d
stmmac_dma_operation_mode	stmmac_main.c	/^static void stmmac_dma_operation_mode(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_dma_ops	hwif.h	/^struct stmmac_dma_ops {$/;"	s
stmmac_dma_qmode	hwif.h	/^#define stmmac_dma_qmode(/;"	d
stmmac_dma_rx_mode	hwif.h	/^#define stmmac_dma_rx_mode(/;"	d
stmmac_dma_tx_mode	hwif.h	/^#define stmmac_dma_tx_mode(/;"	d
stmmac_do_callback	hwif.h	/^#define stmmac_do_callback(/;"	d
stmmac_do_void_callback	hwif.h	/^#define stmmac_do_void_callback(/;"	d
stmmac_dt_phy	stmmac_platform.c	/^static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,$/;"	f	typeref:typename:int	file:
stmmac_dump_dma_regs	hwif.h	/^#define stmmac_dump_dma_regs(/;"	d
stmmac_dump_mac_regs	hwif.h	/^#define stmmac_dump_mac_regs(/;"	d
stmmac_dvr_probe	stmmac_main.c	/^int stmmac_dvr_probe(struct device *device,$/;"	f	typeref:typename:int
stmmac_dvr_remove	stmmac_main.c	/^int stmmac_dvr_remove(struct device *dev)$/;"	f	typeref:typename:int
stmmac_dwmac1_quirks	hwif.c	/^static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_dwmac4_get_mac_addr	dwmac4_lib.c	/^void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,$/;"	f	typeref:typename:void
stmmac_dwmac4_quirks	hwif.c	/^static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_dwmac4_set_mac	dwmac4_lib.c	/^void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void
stmmac_dwmac4_set_mac_addr	dwmac4_lib.c	/^void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],$/;"	f	typeref:typename:void
stmmac_dwmac_mode_quirk	hwif.c	/^static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_dwxlgmac_quirks	hwif.c	/^static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_eee_ctrl_timer	stmmac_main.c	/^static void stmmac_eee_ctrl_timer(struct timer_list *t)$/;"	f	typeref:typename:void	file:
stmmac_eee_init	stmmac_main.c	/^bool stmmac_eee_init(struct stmmac_priv *priv)$/;"	f	typeref:typename:bool
stmmac_enable	stmmac_ptp.c	/^static int stmmac_enable(struct ptp_clock_info *ptp,$/;"	f	typeref:typename:int	file:
stmmac_enable_all_queues	stmmac_main.c	/^static void stmmac_enable_all_queues(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_enable_dma_irq	hwif.h	/^#define stmmac_enable_dma_irq(/;"	d
stmmac_enable_dma_transmission	hwif.h	/^#define stmmac_enable_dma_transmission(/;"	d
stmmac_enable_eee_mode	stmmac_main.c	/^static void stmmac_enable_eee_mode(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_enable_sph	hwif.h	/^#define stmmac_enable_sph(/;"	d
stmmac_enable_tbs	hwif.h	/^#define stmmac_enable_tbs(/;"	d
stmmac_enable_tso	hwif.h	/^#define stmmac_enable_tso(/;"	d
stmmac_enable_tx_timestamp	hwif.h	/^#define stmmac_enable_tx_timestamp(/;"	d
stmmac_enable_vlan	hwif.h	/^#define stmmac_enable_vlan(/;"	d
stmmac_est_configure	hwif.h	/^#define stmmac_est_configure(/;"	d
stmmac_ethtool_get_link_ksettings	stmmac_ethtool.c	/^static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_ethtool_get_regs_len	stmmac_ethtool.c	/^static int stmmac_ethtool_get_regs_len(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_ethtool_getdrvinfo	stmmac_ethtool.c	/^static void stmmac_ethtool_getdrvinfo(struct net_device *dev,$/;"	f	typeref:typename:void	file:
stmmac_ethtool_getmsglevel	stmmac_ethtool.c	/^static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)$/;"	f	typeref:typename:u32	file:
stmmac_ethtool_gregs	stmmac_ethtool.c	/^static void stmmac_ethtool_gregs(struct net_device *dev,$/;"	f	typeref:typename:void	file:
stmmac_ethtool_op_get_eee	stmmac_ethtool.c	/^static int stmmac_ethtool_op_get_eee(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_ethtool_op_set_eee	stmmac_ethtool.c	/^static int stmmac_ethtool_op_set_eee(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_ethtool_ops	stmmac_ethtool.c	/^static const struct ethtool_ops stmmac_ethtool_ops = {$/;"	v	typeref:typename:const struct ethtool_ops	file:
stmmac_ethtool_set_link_ksettings	stmmac_ethtool.c	/^stmmac_ethtool_set_link_ksettings(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_ethtool_setmsglevel	stmmac_ethtool.c	/^static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)$/;"	f	typeref:typename:void	file:
stmmac_exit	stmmac_main.c	/^static void __exit stmmac_exit(void)$/;"	f	typeref:typename:void __exit	file:
stmmac_exit_fs	stmmac_main.c	/^static void stmmac_exit_fs(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_extra_stats	common.h	/^struct stmmac_extra_stats {$/;"	s
stmmac_filter_check	stmmac_selftests.c	/^static int stmmac_filter_check(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_fix_features	stmmac_main.c	/^static netdev_features_t stmmac_fix_features(struct net_device *dev,$/;"	f	typeref:typename:netdev_features_t	file:
stmmac_flex_pps_config	hwif.h	/^#define stmmac_flex_pps_config(/;"	d
stmmac_flow_ctrl	hwif.h	/^#define stmmac_flow_ctrl(/;"	d
stmmac_flow_entry	stmmac.h	/^struct stmmac_flow_entry {$/;"	s
stmmac_fpe_configure	hwif.h	/^#define stmmac_fpe_configure(/;"	d
stmmac_free_rx_buffer	stmmac_main.c	/^static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)$/;"	f	typeref:typename:void	file:
stmmac_free_tx_buffer	stmmac_main.c	/^static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)$/;"	f	typeref:typename:void	file:
stmmac_free_tx_skbufs	stmmac_main.c	/^static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_fs_dir	stmmac_main.c	/^static struct dentry *stmmac_fs_dir;$/;"	v	typeref:struct:dentry *	file:
stmmac_get_channels	stmmac_ethtool.c	/^static void stmmac_get_channels(struct net_device *dev,$/;"	f	typeref:typename:void	file:
stmmac_get_coalesce	stmmac_ethtool.c	/^static int stmmac_get_coalesce(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_get_desc_addr	hwif.h	/^#define stmmac_get_desc_addr(/;"	d
stmmac_get_dev_id	hwif.c	/^static u32 stmmac_get_dev_id(struct stmmac_priv *priv, u32 id_reg)$/;"	f	typeref:typename:u32	file:
stmmac_get_ethtool_stats	stmmac_ethtool.c	/^static void stmmac_get_ethtool_stats(struct net_device *dev,$/;"	f	typeref:typename:void	file:
stmmac_get_hw_feature	hwif.h	/^#define stmmac_get_hw_feature(/;"	d
stmmac_get_hw_features	stmmac_main.c	/^static int stmmac_get_hw_features(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_get_id	hwif.c	/^static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)$/;"	f	typeref:typename:u32	file:
stmmac_get_mac_addr	dwmac_lib.c	/^void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,$/;"	f	typeref:typename:void
stmmac_get_mac_tx_timestamp	hwif.h	/^#define stmmac_get_mac_tx_timestamp(/;"	d
stmmac_get_pauseparam	stmmac_ethtool.c	/^stmmac_get_pauseparam(struct net_device *netdev,$/;"	f	typeref:typename:void	file:
stmmac_get_platform_resources	stmmac_platform.c	/^int stmmac_get_platform_resources(struct platform_device *pdev,$/;"	f	typeref:typename:int
stmmac_get_ringparam	stmmac_ethtool.c	/^static void stmmac_get_ringparam(struct net_device *netdev,$/;"	f	typeref:typename:void	file:
stmmac_get_rx_frame_len	hwif.h	/^#define stmmac_get_rx_frame_len(/;"	d
stmmac_get_rx_hash	hwif.h	/^#define stmmac_get_rx_hash(/;"	d
stmmac_get_rx_header_len	hwif.h	/^#define stmmac_get_rx_header_len(/;"	d
stmmac_get_rx_hwtstamp	stmmac_main.c	/^static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,$/;"	f	typeref:typename:void	file:
stmmac_get_rx_timestamp_status	hwif.h	/^#define stmmac_get_rx_timestamp_status(/;"	d
stmmac_get_rxfh	stmmac_ethtool.c	/^static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,$/;"	f	typeref:typename:int	file:
stmmac_get_rxfh_indir_size	stmmac_ethtool.c	/^static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)$/;"	f	typeref:typename:u32	file:
stmmac_get_rxfh_key_size	stmmac_ethtool.c	/^static u32 stmmac_get_rxfh_key_size(struct net_device *dev)$/;"	f	typeref:typename:u32	file:
stmmac_get_rxnfc	stmmac_ethtool.c	/^static int stmmac_get_rxnfc(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_get_sset_count	stmmac_ethtool.c	/^static int stmmac_get_sset_count(struct net_device *netdev, int sset)$/;"	f	typeref:typename:int	file:
stmmac_get_strings	stmmac_ethtool.c	/^static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)$/;"	f	typeref:typename:void	file:
stmmac_get_systime	hwif.h	/^#define stmmac_get_systime(/;"	d
stmmac_get_time	stmmac_ptp.c	/^static int stmmac_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)$/;"	f	typeref:typename:int	file:
stmmac_get_timestamp	hwif.h	/^#define stmmac_get_timestamp(/;"	d
stmmac_get_ts_info	stmmac_ethtool.c	/^static int stmmac_get_ts_info(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_get_tunable	stmmac_ethtool.c	/^static int stmmac_get_tunable(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_get_tx_hwtstamp	stmmac_main.c	/^static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,$/;"	f	typeref:typename:void	file:
stmmac_get_tx_len	hwif.h	/^#define stmmac_get_tx_len(/;"	d
stmmac_get_tx_ls	hwif.h	/^#define stmmac_get_tx_ls(/;"	d
stmmac_get_tx_owner	hwif.h	/^#define stmmac_get_tx_owner(/;"	d
stmmac_get_tx_timestamp_status	hwif.h	/^#define stmmac_get_tx_timestamp_status(/;"	d
stmmac_get_umac_addr	hwif.h	/^#define stmmac_get_umac_addr(/;"	d
stmmac_get_wol	stmmac_ethtool.c	/^static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)$/;"	f	typeref:typename:void	file:
stmmac_global_err	stmmac_main.c	/^static void stmmac_global_err(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_gstrings_stats	stmmac_ethtool.c	/^static const struct stmmac_stats stmmac_gstrings_stats[] = {$/;"	v	typeref:typename:const struct stmmac_stats[]	file:
stmmac_hash_check	stmmac_selftests.c	/^static bool stmmac_hash_check(struct stmmac_priv *priv, unsigned char *addr)$/;"	f	typeref:typename:bool	file:
stmmac_host_irq_status	hwif.h	/^#define stmmac_host_irq_status(/;"	d
stmmac_host_mtl_irq_status	hwif.h	/^#define stmmac_host_mtl_irq_status(/;"	d
stmmac_hw	hwif.c	/^} stmmac_hw[] = {$/;"	v	typeref:typename:const struct stmmac_hwif_entry[]
stmmac_hw_init	stmmac_main.c	/^static int stmmac_hw_init(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_hw_setup	stmmac_main.c	/^static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)$/;"	f	typeref:typename:int	file:
stmmac_hw_teardown	stmmac_main.c	/^static void stmmac_hw_teardown(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_hwif_entry	hwif.c	/^static const struct stmmac_hwif_entry {$/;"	s	file:
stmmac_hwif_init	hwif.c	/^int stmmac_hwif_init(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
stmmac_hwtimestamp	hwif.h	/^struct stmmac_hwtimestamp {$/;"	s
stmmac_hwtstamp_get	stmmac_main.c	/^static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)$/;"	f	typeref:typename:int	file:
stmmac_hwtstamp_set	stmmac_main.c	/^static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)$/;"	f	typeref:typename:int	file:
stmmac_id_table	stmmac_pci.c	/^static const struct pci_device_id stmmac_id_table[] = {$/;"	v	typeref:typename:const struct pci_device_id[]	file:
stmmac_init	stmmac_main.c	/^static int __init stmmac_init(void)$/;"	f	typeref:typename:int __init	file:
stmmac_init_chan	hwif.h	/^#define stmmac_init_chan(/;"	d
stmmac_init_coalesce	stmmac_main.c	/^static void stmmac_init_coalesce(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_init_desc3	hwif.h	/^#define stmmac_init_desc3(/;"	d
stmmac_init_dma_engine	stmmac_main.c	/^static int stmmac_init_dma_engine(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_init_fs	stmmac_main.c	/^static void stmmac_init_fs(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_init_phy	stmmac_main.c	/^static int stmmac_init_phy(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_init_ptp	stmmac_main.c	/^static int stmmac_init_ptp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_init_rx_buffers	stmmac_main.c	/^static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,$/;"	f	typeref:typename:int	file:
stmmac_init_rx_chan	hwif.h	/^#define stmmac_init_rx_chan(/;"	d
stmmac_init_rx_desc	hwif.h	/^#define stmmac_init_rx_desc(/;"	d
stmmac_init_systime	hwif.h	/^#define stmmac_init_systime(/;"	d
stmmac_init_tstamp_counter	stmmac_main.c	/^int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)$/;"	f	typeref:typename:int
stmmac_init_tx_chan	hwif.h	/^#define stmmac_init_tx_chan(/;"	d
stmmac_init_tx_desc	hwif.h	/^#define stmmac_init_tx_desc(/;"	d
stmmac_interrupt	stmmac_main.c	/^static irqreturn_t stmmac_interrupt(int irq, void *dev_id)$/;"	f	typeref:typename:irqreturn_t	file:
stmmac_ioctl	stmmac_main.c	/^static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)$/;"	f	typeref:typename:int	file:
stmmac_is_jumbo_frm	hwif.h	/^#define stmmac_is_jumbo_frm(/;"	d
stmmac_jumbo_frm	hwif.h	/^#define stmmac_jumbo_frm(/;"	d
stmmac_mac_an_restart	stmmac_main.c	/^static void stmmac_mac_an_restart(struct phylink_config *config)$/;"	f	typeref:typename:void	file:
stmmac_mac_config	stmmac_main.c	/^static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,$/;"	f	typeref:typename:void	file:
stmmac_mac_config_rss	stmmac_main.c	/^static void stmmac_mac_config_rss(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mac_config_rx_queues_prio	stmmac_main.c	/^static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mac_config_rx_queues_routing	stmmac_main.c	/^static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mac_config_tx_queues_prio	stmmac_main.c	/^static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mac_debug	hwif.h	/^#define stmmac_mac_debug(/;"	d
stmmac_mac_enable_rx_queues	stmmac_main.c	/^static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mac_flow_ctrl	stmmac_main.c	/^static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)$/;"	f	typeref:typename:void	file:
stmmac_mac_link_down	stmmac_main.c	/^static void stmmac_mac_link_down(struct phylink_config *config,$/;"	f	typeref:typename:void	file:
stmmac_mac_link_up	stmmac_main.c	/^static void stmmac_mac_link_up(struct phylink_config *config,$/;"	f	typeref:typename:void	file:
stmmac_mac_pcs_get_state	stmmac_main.c	/^static void stmmac_mac_pcs_get_state(struct phylink_config *config,$/;"	f	typeref:typename:void	file:
stmmac_mac_set	hwif.h	/^#define stmmac_mac_set(/;"	d
stmmac_map_mtl_to_dma	hwif.h	/^#define stmmac_map_mtl_to_dma(/;"	d
stmmac_mdio_read	stmmac_mdio.c	/^static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)$/;"	f	typeref:typename:int	file:
stmmac_mdio_register	stmmac_mdio.c	/^int stmmac_mdio_register(struct net_device *ndev)$/;"	f	typeref:typename:int
stmmac_mdio_reset	stmmac_mdio.c	/^int stmmac_mdio_reset(struct mii_bus *bus)$/;"	f	typeref:typename:int
stmmac_mdio_unregister	stmmac_mdio.c	/^int stmmac_mdio_unregister(struct net_device *ndev)$/;"	f	typeref:typename:int
stmmac_mdio_write	stmmac_mdio.c	/^static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,$/;"	f	typeref:typename:int	file:
stmmac_mmc	stmmac_ethtool.c	/^static const struct stmmac_stats stmmac_mmc[] = {$/;"	v	typeref:typename:const struct stmmac_stats[]	file:
stmmac_mmc_ctrl	hwif.h	/^#define stmmac_mmc_ctrl(/;"	d
stmmac_mmc_intr_all_mask	hwif.h	/^#define stmmac_mmc_intr_all_mask(/;"	d
stmmac_mmc_ops	hwif.h	/^struct stmmac_mmc_ops {$/;"	s
stmmac_mmc_read	hwif.h	/^#define stmmac_mmc_read(/;"	d
stmmac_mmc_setup	stmmac_main.c	/^static void stmmac_mmc_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mode_init	hwif.h	/^#define stmmac_mode_init(/;"	d
stmmac_mode_ops	hwif.h	/^struct stmmac_mode_ops {$/;"	s
stmmac_mtl_configuration	stmmac_main.c	/^static void stmmac_mtl_configuration(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_mtl_setup	stmmac_platform.c	/^static int stmmac_mtl_setup(struct platform_device *pdev,$/;"	f	typeref:typename:int	file:
stmmac_mtl_setup_acpi	stmmac_platform.c	/^static void stmmac_mtl_setup_acpi(struct platform_device *pdev,$/;"	f	typeref:typename:void	file:
stmmac_napi_add	stmmac_main.c	/^static void stmmac_napi_add(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_napi_check	stmmac_main.c	/^static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:int	file:
stmmac_napi_del	stmmac_main.c	/^static void stmmac_napi_del(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_napi_poll_rx	stmmac_main.c	/^static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)$/;"	f	typeref:typename:int	file:
stmmac_napi_poll_tx	stmmac_main.c	/^static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)$/;"	f	typeref:typename:int	file:
stmmac_netdev_ops	stmmac_main.c	/^static const struct net_device_ops stmmac_netdev_ops = {$/;"	v	typeref:typename:const struct net_device_ops	file:
stmmac_netdev_ops	stmmac_main.c	/^static const struct net_device_ops stmmac_netdev_ops;$/;"	v	typeref:typename:const struct net_device_ops	file:
stmmac_notifier	stmmac_main.c	/^static struct notifier_block stmmac_notifier = {$/;"	v	typeref:struct:notifier_block	file:
stmmac_nway_reset	stmmac_ethtool.c	/^static int stmmac_nway_reset(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_ocp_rst	dwmac-socfpga.c	/^	struct reset_control *stmmac_ocp_rst;$/;"	m	struct:socfpga_dwmac	typeref:struct:reset_control *	file:
stmmac_of_get_mac_mode	stmmac_platform.c	/^static int stmmac_of_get_mac_mode(struct device_node *np)$/;"	f	typeref:typename:int	file:
stmmac_open	stmmac_main.c	/^static int stmmac_open(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_ops	hwif.h	/^struct stmmac_ops {$/;"	s
stmmac_packet_attrs	stmmac_selftests.c	/^struct stmmac_packet_attrs {$/;"	s	file:
stmmac_pci_dmi_data	dwmac-intel.c	/^struct stmmac_pci_dmi_data {$/;"	s	file:
stmmac_pci_driver	stmmac_pci.c	/^static struct pci_driver stmmac_pci_driver = {$/;"	v	typeref:struct:pci_driver	file:
stmmac_pci_find_phy_addr	dwmac-intel.c	/^static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
stmmac_pci_func_data	dwmac-intel.c	/^struct stmmac_pci_func_data {$/;"	s	file:
stmmac_pci_info	dwmac-intel.c	/^struct stmmac_pci_info {$/;"	s	file:
stmmac_pci_info	stmmac_pci.c	/^static const struct stmmac_pci_info stmmac_pci_info = {$/;"	v	typeref:typename:const struct stmmac_pci_info	file:
stmmac_pci_info	stmmac_pci.c	/^struct stmmac_pci_info {$/;"	s	file:
stmmac_pci_probe	stmmac_pci.c	/^static int stmmac_pci_probe(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
stmmac_pci_remove	stmmac_pci.c	/^static void stmmac_pci_remove(struct pci_dev *pdev)$/;"	f	typeref:typename:void	file:
stmmac_pci_resume	stmmac_pci.c	/^static int __maybe_unused stmmac_pci_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pci_suspend	stmmac_pci.c	/^static int __maybe_unused stmmac_pci_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pcs_ctrl_ane	hwif.h	/^#define stmmac_pcs_ctrl_ane(/;"	d
stmmac_pcs_get_adv_lp	hwif.h	/^#define stmmac_pcs_get_adv_lp(/;"	d
stmmac_pcs_rane	hwif.h	/^#define stmmac_pcs_rane(/;"	d
stmmac_perfect_check	stmmac_selftests.c	/^static bool stmmac_perfect_check(struct stmmac_priv *priv, unsigned char *addr)$/;"	f	typeref:typename:bool	file:
stmmac_phy_setup	stmmac_main.c	/^static int stmmac_phy_setup(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_phylink_mac_ops	stmmac_main.c	/^static const struct phylink_mac_ops stmmac_phylink_mac_ops = {$/;"	v	typeref:typename:const struct phylink_mac_ops	file:
stmmac_pltfr_noirq_resume	stmmac_platform.c	/^static int __maybe_unused stmmac_pltfr_noirq_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pltfr_noirq_suspend	stmmac_platform.c	/^static int __maybe_unused stmmac_pltfr_noirq_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pltfr_pm_ops	stmmac_platform.c	/^const struct dev_pm_ops stmmac_pltfr_pm_ops = {$/;"	v	typeref:typename:const struct dev_pm_ops
stmmac_pltfr_remove	stmmac_platform.c	/^int stmmac_pltfr_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int
stmmac_pltfr_resume	stmmac_platform.c	/^static int __maybe_unused stmmac_pltfr_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pltfr_suspend	stmmac_platform.c	/^static int __maybe_unused stmmac_pltfr_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_pmt	hwif.h	/^#define stmmac_pmt(/;"	d
stmmac_poll_controller	stmmac_main.c	/^static void stmmac_poll_controller(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_pps_cfg	stmmac.h	/^struct stmmac_pps_cfg {$/;"	s
stmmac_prepare_tso_tx_desc	hwif.h	/^#define stmmac_prepare_tso_tx_desc(/;"	d
stmmac_prepare_tx_desc	hwif.h	/^#define stmmac_prepare_tx_desc(/;"	d
stmmac_priv	stmmac.h	/^struct stmmac_priv {$/;"	s
stmmac_probe_config_acpi	stmmac_platform.c	/^stmmac_probe_config_acpi(struct platform_device *pdev, const char **mac)$/;"	f	typeref:struct:plat_stmmacenet_data *
stmmac_probe_config_dt	stmmac_platform.c	/^stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)$/;"	f	typeref:struct:plat_stmmacenet_data *
stmmac_prog_mtl_rx_algorithms	hwif.h	/^#define stmmac_prog_mtl_rx_algorithms(/;"	d
stmmac_prog_mtl_tx_algorithms	hwif.h	/^#define stmmac_prog_mtl_tx_algorithms(/;"	d
stmmac_ptp	stmmac_hwtstamp.c	/^const struct stmmac_hwtimestamp stmmac_ptp = {$/;"	v	typeref:typename:const struct stmmac_hwtimestamp
stmmac_ptp_clock_ops	stmmac_ptp.c	/^static struct ptp_clock_info stmmac_ptp_clock_ops = {$/;"	v	typeref:struct:ptp_clock_info	file:
stmmac_ptp_register	stmmac_ptp.c	/^void stmmac_ptp_register(struct stmmac_priv *priv)$/;"	f	typeref:typename:void
stmmac_ptp_unregister	stmmac_ptp.c	/^void stmmac_ptp_unregister(struct stmmac_priv *priv)$/;"	f	typeref:typename:void
stmmac_refill_desc3	hwif.h	/^#define stmmac_refill_desc3(/;"	d
stmmac_regs_off	hwif.h	/^struct stmmac_regs_off {$/;"	s
stmmac_reinit_queues	stmmac_main.c	/^int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)$/;"	f	typeref:typename:int
stmmac_reinit_ringparam	stmmac_main.c	/^int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)$/;"	f	typeref:typename:int
stmmac_release	stmmac_main.c	/^static int stmmac_release(struct net_device *dev)$/;"	f	typeref:typename:int	file:
stmmac_release_ptp	stmmac_main.c	/^static void stmmac_release_ptp(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_release_tx_desc	hwif.h	/^#define stmmac_release_tx_desc(/;"	d
stmmac_remove_config_dt	stmmac_platform.c	/^void stmmac_remove_config_dt(struct platform_device *pdev,$/;"	f	typeref:typename:void
stmmac_reset	hwif.h	/^#define stmmac_reset(/;"	d
stmmac_reset_eee_mode	hwif.h	/^#define stmmac_reset_eee_mode(/;"	d
stmmac_reset_queues_param	stmmac_main.c	/^static void stmmac_reset_queues_param(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_reset_subtask	stmmac_main.c	/^static void stmmac_reset_subtask(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_resources	stmmac.h	/^struct stmmac_resources {$/;"	s
stmmac_restore_hw_vlan_rx_fltr	hwif.h	/^#define stmmac_restore_hw_vlan_rx_fltr(/;"	d
stmmac_resume	stmmac_main.c	/^int stmmac_resume(struct device *dev)$/;"	f	typeref:typename:int
stmmac_rings_status_show	stmmac_main.c	/^static int stmmac_rings_status_show(struct seq_file *seq, void *v)$/;"	f	typeref:typename:int	file:
stmmac_riwt2usec	stmmac_ethtool.c	/^static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)$/;"	f	typeref:typename:u32	file:
stmmac_rss	stmmac.h	/^struct stmmac_rss {$/;"	s
stmmac_rss_configure	hwif.h	/^#define stmmac_rss_configure(/;"	d
stmmac_rst	dwmac-socfpga.c	/^	struct reset_control *stmmac_rst;$/;"	m	struct:socfpga_dwmac	typeref:struct:reset_control *	file:
stmmac_runtime_resume	stmmac_platform.c	/^static int __maybe_unused stmmac_runtime_resume(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_runtime_suspend	stmmac_platform.c	/^static int __maybe_unused stmmac_runtime_suspend(struct device *dev)$/;"	f	typeref:typename:int __maybe_unused	file:
stmmac_rx	stmmac_main.c	/^static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)$/;"	f	typeref:typename:int	file:
stmmac_rx_buf1_len	stmmac_main.c	/^static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,$/;"	f	typeref:typename:unsigned int	file:
stmmac_rx_buf2_len	stmmac_main.c	/^static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,$/;"	f	typeref:typename:unsigned int	file:
stmmac_rx_buffer	stmmac.h	/^struct stmmac_rx_buffer {$/;"	s
stmmac_rx_dirty	stmmac_main.c	/^static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:u32	file:
stmmac_rx_extended_status	hwif.h	/^#define stmmac_rx_extended_status(/;"	d
stmmac_rx_ipc	hwif.h	/^#define stmmac_rx_ipc(/;"	d
stmmac_rx_queue	stmmac.h	/^struct stmmac_rx_queue {$/;"	s
stmmac_rx_queue_dma_chan_map	stmmac_main.c	/^static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_rx_queue_enable	hwif.h	/^#define stmmac_rx_queue_enable(/;"	d
stmmac_rx_queue_prio	hwif.h	/^#define stmmac_rx_queue_prio(/;"	d
stmmac_rx_queue_routing	hwif.h	/^#define stmmac_rx_queue_routing(/;"	d
stmmac_rx_refill	stmmac_main.c	/^static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
stmmac_rx_routing	common.h	/^struct stmmac_rx_routing {$/;"	s
stmmac_rx_status	hwif.h	/^#define stmmac_rx_status(/;"	d
stmmac_rx_vlan	stmmac_main.c	/^static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)$/;"	f	typeref:typename:void	file:
stmmac_rx_watchdog	hwif.h	/^#define stmmac_rx_watchdog(/;"	d
stmmac_rxp_config	hwif.h	/^#define stmmac_rxp_config(/;"	d
stmmac_safety_feat_config	hwif.h	/^#define stmmac_safety_feat_config(/;"	d
stmmac_safety_feat_configuration	stmmac_main.c	/^static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_safety_feat_dump	hwif.h	/^#define stmmac_safety_feat_dump(/;"	d
stmmac_safety_feat_interrupt	stmmac_main.c	/^static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)$/;"	f	typeref:typename:bool	file:
stmmac_safety_feat_irq_status	hwif.h	/^#define stmmac_safety_feat_irq_status(/;"	d
stmmac_safety_stats	common.h	/^struct stmmac_safety_stats {$/;"	s
stmmac_sarc_configure	hwif.h	/^#define stmmac_sarc_configure(/;"	d
stmmac_select_queue	stmmac_main.c	/^static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,$/;"	f	typeref:typename:u16	file:
stmmac_selftest_get_count	stmmac.h	/^static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
stmmac_selftest_get_count	stmmac_selftests.c	/^int stmmac_selftest_get_count(struct stmmac_priv *priv)$/;"	f	typeref:typename:int
stmmac_selftest_get_strings	stmmac.h	/^static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,$/;"	f	typeref:typename:void
stmmac_selftest_get_strings	stmmac_selftests.c	/^void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data)$/;"	f	typeref:typename:void
stmmac_selftest_run	stmmac.h	/^static inline void stmmac_selftest_run(struct net_device *dev,$/;"	f	typeref:typename:void
stmmac_selftest_run	stmmac_selftests.c	/^void stmmac_selftest_run(struct net_device *dev,$/;"	f	typeref:typename:void
stmmac_selftests	stmmac_selftests.c	/^} stmmac_selftests[] = {$/;"	v	typeref:typename:const struct stmmac_test[]
stmmac_service_event_schedule	stmmac_main.c	/^static void stmmac_service_event_schedule(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_service_task	stmmac_main.c	/^static void stmmac_service_task(struct work_struct *work)$/;"	f	typeref:typename:void	file:
stmmac_set_16kib_bfsize	hwif.h	/^#define stmmac_set_16kib_bfsize(/;"	d
stmmac_set_arp_offload	hwif.h	/^#define stmmac_set_arp_offload(/;"	d
stmmac_set_bfsize	stmmac_main.c	/^static int stmmac_set_bfsize(int mtu, int bufsize)$/;"	f	typeref:typename:int	file:
stmmac_set_channels	stmmac_ethtool.c	/^static int stmmac_set_channels(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_set_coalesce	stmmac_ethtool.c	/^static int stmmac_set_coalesce(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_set_desc_addr	hwif.h	/^#define stmmac_set_desc_addr(/;"	d
stmmac_set_desc_sarc	hwif.h	/^#define stmmac_set_desc_sarc(/;"	d
stmmac_set_desc_sec_addr	hwif.h	/^#define stmmac_set_desc_sec_addr(/;"	d
stmmac_set_desc_tbs	hwif.h	/^#define stmmac_set_desc_tbs(/;"	d
stmmac_set_desc_vlan	hwif.h	/^#define stmmac_set_desc_vlan(/;"	d
stmmac_set_desc_vlan_tag	hwif.h	/^#define stmmac_set_desc_vlan_tag(/;"	d
stmmac_set_dma_bfsize	hwif.h	/^#define stmmac_set_dma_bfsize(/;"	d
stmmac_set_dma_operation_mode	stmmac_main.c	/^static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,$/;"	f	typeref:typename:void	file:
stmmac_set_eee_mode	hwif.h	/^#define stmmac_set_eee_mode(/;"	d
stmmac_set_eee_pls	hwif.h	/^#define stmmac_set_eee_pls(/;"	d
stmmac_set_eee_timer	hwif.h	/^#define stmmac_set_eee_timer(/;"	d
stmmac_set_ethtool_ops	stmmac_ethtool.c	/^void stmmac_set_ethtool_ops(struct net_device *netdev)$/;"	f	typeref:typename:void
stmmac_set_features	stmmac_main.c	/^static int stmmac_set_features(struct net_device *netdev,$/;"	f	typeref:typename:int	file:
stmmac_set_filter	hwif.h	/^#define stmmac_set_filter(/;"	d
stmmac_set_mac	dwmac_lib.c	/^void stmmac_set_mac(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void
stmmac_set_mac_addr	dwmac_lib.c	/^void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],$/;"	f	typeref:typename:void
stmmac_set_mac_address	stmmac_main.c	/^static int stmmac_set_mac_address(struct net_device *ndev, void *addr)$/;"	f	typeref:typename:int	file:
stmmac_set_mac_loopback	hwif.h	/^#define stmmac_set_mac_loopback(/;"	d
stmmac_set_mss	hwif.h	/^#define stmmac_set_mss(/;"	d
stmmac_set_mtl_tx_queue_weight	hwif.h	/^#define stmmac_set_mtl_tx_queue_weight(/;"	d
stmmac_set_pauseparam	stmmac_ethtool.c	/^stmmac_set_pauseparam(struct net_device *netdev,$/;"	f	typeref:typename:int	file:
stmmac_set_ringparam	stmmac_ethtool.c	/^static int stmmac_set_ringparam(struct net_device *netdev,$/;"	f	typeref:typename:int	file:
stmmac_set_rings_length	stmmac_main.c	/^static void stmmac_set_rings_length(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_set_rx_mode	stmmac_main.c	/^static void stmmac_set_rx_mode(struct net_device *dev)$/;"	f	typeref:typename:void	file:
stmmac_set_rx_owner	hwif.h	/^#define stmmac_set_rx_owner(/;"	d
stmmac_set_rx_ring_len	hwif.h	/^#define stmmac_set_rx_ring_len(/;"	d
stmmac_set_rx_tail_ptr	hwif.h	/^#define stmmac_set_rx_tail_ptr(/;"	d
stmmac_set_rxfh	stmmac_ethtool.c	/^static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,$/;"	f	typeref:typename:int	file:
stmmac_set_time	stmmac_ptp.c	/^static int stmmac_set_time(struct ptp_clock_info *ptp,$/;"	f	typeref:typename:int	file:
stmmac_set_tunable	stmmac_ethtool.c	/^static int stmmac_set_tunable(struct net_device *dev,$/;"	f	typeref:typename:int	file:
stmmac_set_tx_ic	hwif.h	/^#define stmmac_set_tx_ic(/;"	d
stmmac_set_tx_owner	hwif.h	/^#define stmmac_set_tx_owner(/;"	d
stmmac_set_tx_queue_weight	stmmac_main.c	/^static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_set_tx_ring_len	hwif.h	/^#define stmmac_set_tx_ring_len(/;"	d
stmmac_set_tx_tail_ptr	hwif.h	/^#define stmmac_set_tx_tail_ptr(/;"	d
stmmac_set_umac_addr	hwif.h	/^#define stmmac_set_umac_addr(/;"	d
stmmac_set_wol	stmmac_ethtool.c	/^static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)$/;"	f	typeref:typename:int	file:
stmmac_setup_tc	stmmac_main.c	/^static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,$/;"	f	typeref:typename:int	file:
stmmac_setup_tc_block_cb	stmmac_main.c	/^static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,$/;"	f	typeref:typename:int	file:
stmmac_start_all_dma	stmmac_main.c	/^static void stmmac_start_all_dma(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_start_rx	hwif.h	/^#define stmmac_start_rx(/;"	d
stmmac_start_rx_dma	stmmac_main.c	/^static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:void	file:
stmmac_start_tx	hwif.h	/^#define stmmac_start_tx(/;"	d
stmmac_start_tx_dma	stmmac_main.c	/^static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:void	file:
stmmac_state	stmmac.h	/^enum stmmac_state {$/;"	g
stmmac_stats	stmmac_ethtool.c	/^struct stmmac_stats {$/;"	s	file:
stmmac_stop_all_dma	stmmac_main.c	/^static void stmmac_stop_all_dma(struct stmmac_priv *priv)$/;"	f	typeref:typename:void	file:
stmmac_stop_rx	hwif.h	/^#define stmmac_stop_rx(/;"	d
stmmac_stop_rx_dma	stmmac_main.c	/^static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:void	file:
stmmac_stop_tx	hwif.h	/^#define stmmac_stop_tx(/;"	d
stmmac_stop_tx_dma	stmmac_main.c	/^static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:void	file:
stmmac_suspend	stmmac_main.c	/^int stmmac_suspend(struct device *dev)$/;"	f	typeref:typename:int
stmmac_tc_entry	stmmac.h	/^struct stmmac_tc_entry {$/;"	s
stmmac_tc_init	hwif.h	/^#define stmmac_tc_init(/;"	d
stmmac_tc_ops	hwif.h	/^struct stmmac_tc_ops {$/;"	s
stmmac_tc_setup_cbs	hwif.h	/^#define stmmac_tc_setup_cbs(/;"	d
stmmac_tc_setup_cls	hwif.h	/^#define stmmac_tc_setup_cls(/;"	d
stmmac_tc_setup_cls_u32	hwif.h	/^#define stmmac_tc_setup_cls_u32(/;"	d
stmmac_tc_setup_etf	hwif.h	/^#define stmmac_tc_setup_etf(/;"	d
stmmac_tc_setup_taprio	hwif.h	/^#define stmmac_tc_setup_taprio(/;"	d
stmmac_test	stmmac_selftests.c	/^static const struct stmmac_test {$/;"	s	file:
stmmac_test_arp_validate	stmmac_selftests.c	/^static int stmmac_test_arp_validate(struct sk_buff *skb,$/;"	f	typeref:typename:int	file:
stmmac_test_arpoffload	stmmac_selftests.c	/^static int stmmac_test_arpoffload(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_desc_sai	stmmac_selftests.c	/^static int stmmac_test_desc_sai(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_desc_sar	stmmac_selftests.c	/^static int stmmac_test_desc_sar(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_dvlanfilt	stmmac_selftests.c	/^static int stmmac_test_dvlanfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_dvlanfilt_perfect	stmmac_selftests.c	/^static int stmmac_test_dvlanfilt_perfect(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_eee	stmmac_selftests.c	/^static int stmmac_test_eee(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_flowctrl	stmmac_selftests.c	/^static int stmmac_test_flowctrl(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_flowctrl_validate	stmmac_selftests.c	/^static int stmmac_test_flowctrl_validate(struct sk_buff *skb,$/;"	f	typeref:typename:int	file:
stmmac_test_get_arp_skb	stmmac_selftests.c	/^static struct sk_buff *stmmac_test_get_arp_skb(struct stmmac_priv *priv,$/;"	f	typeref:struct:sk_buff *	file:
stmmac_test_get_udp_skb	stmmac_selftests.c	/^static struct sk_buff *stmmac_test_get_udp_skb(struct stmmac_priv *priv,$/;"	f	typeref:struct:sk_buff *	file:
stmmac_test_hfilt	stmmac_selftests.c	/^static int stmmac_test_hfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_jumbo	stmmac_selftests.c	/^static int stmmac_test_jumbo(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l3filt_da	stmmac_selftests.c	/^static int stmmac_test_l3filt_da(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l3filt_sa	stmmac_selftests.c	/^static int stmmac_test_l3filt_sa(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l4filt_da_tcp	stmmac_selftests.c	/^static int stmmac_test_l4filt_da_tcp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l4filt_da_udp	stmmac_selftests.c	/^static int stmmac_test_l4filt_da_udp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l4filt_sa_tcp	stmmac_selftests.c	/^static int stmmac_test_l4filt_sa_tcp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_l4filt_sa_udp	stmmac_selftests.c	/^static int stmmac_test_l4filt_sa_udp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_loopback_validate	stmmac_selftests.c	/^static int stmmac_test_loopback_validate(struct sk_buff *skb,$/;"	f	typeref:typename:int	file:
stmmac_test_mac_loopback	stmmac_selftests.c	/^static int stmmac_test_mac_loopback(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_mcfilt	stmmac_selftests.c	/^static int stmmac_test_mcfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_mjumbo	stmmac_selftests.c	/^static int stmmac_test_mjumbo(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_mmc	stmmac_selftests.c	/^static int stmmac_test_mmc(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_next_id	stmmac_selftests.c	/^static u8 stmmac_test_next_id;$/;"	v	typeref:typename:u8	file:
stmmac_test_pfilt	stmmac_selftests.c	/^static int stmmac_test_pfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_phy_loopback	stmmac_selftests.c	/^static int stmmac_test_phy_loopback(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_priv	stmmac_selftests.c	/^struct stmmac_test_priv {$/;"	s	file:
stmmac_test_reg_sai	stmmac_selftests.c	/^static int stmmac_test_reg_sai(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_reg_sar	stmmac_selftests.c	/^static int stmmac_test_reg_sar(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_rss	stmmac_selftests.c	/^static int stmmac_test_rss(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_rxp	stmmac_selftests.c	/^static int stmmac_test_rxp(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_sph	stmmac_selftests.c	/^static int stmmac_test_sph(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_svlanoff	stmmac_selftests.c	/^static int stmmac_test_svlanoff(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_tbs	stmmac_selftests.c	/^static int stmmac_test_tbs(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_ucfilt	stmmac_selftests.c	/^static int stmmac_test_ucfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_vlan_validate	stmmac_selftests.c	/^static int stmmac_test_vlan_validate(struct sk_buff *skb,$/;"	f	typeref:typename:int	file:
stmmac_test_vlanfilt	stmmac_selftests.c	/^static int stmmac_test_vlanfilt(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_vlanfilt_perfect	stmmac_selftests.c	/^static int stmmac_test_vlanfilt_perfect(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_vlanoff	stmmac_selftests.c	/^static int stmmac_test_vlanoff(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
stmmac_test_vlanoff_common	stmmac_selftests.c	/^static int stmmac_test_vlanoff_common(struct stmmac_priv *priv, bool svlan)$/;"	f	typeref:typename:int	file:
stmmac_tso_allocator	stmmac_main.c	/^static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,$/;"	f	typeref:typename:void	file:
stmmac_tso_xmit	stmmac_main.c	/^static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)$/;"	f	typeref:typename:netdev_tx_t	file:
stmmac_tx_avail	stmmac_main.c	/^static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:u32	file:
stmmac_tx_clean	stmmac_main.c	/^static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)$/;"	f	typeref:typename:int	file:
stmmac_tx_err	stmmac_main.c	/^static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)$/;"	f	typeref:typename:void	file:
stmmac_tx_info	stmmac.h	/^struct stmmac_tx_info {$/;"	s
stmmac_tx_queue	stmmac.h	/^struct stmmac_tx_queue {$/;"	s
stmmac_tx_queue_prio	hwif.h	/^#define stmmac_tx_queue_prio(/;"	d
stmmac_tx_status	hwif.h	/^#define stmmac_tx_status(/;"	d
stmmac_tx_timeout	stmmac_main.c	/^static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)$/;"	f	typeref:typename:void	file:
stmmac_tx_timer	stmmac_main.c	/^static void stmmac_tx_timer(struct timer_list *t)$/;"	f	typeref:typename:void	file:
stmmac_tx_timer_arm	stmmac_main.c	/^static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)$/;"	f	typeref:typename:void	file:
stmmac_update_vlan_hash	hwif.h	/^#define stmmac_update_vlan_hash(/;"	d
stmmac_usec2riwt	stmmac_ethtool.c	/^static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)$/;"	f	typeref:typename:u32	file:
stmmac_validate	stmmac_main.c	/^static void stmmac_validate(struct phylink_config *config,$/;"	f	typeref:typename:void	file:
stmmac_verify_args	stmmac_main.c	/^static void stmmac_verify_args(void)$/;"	f	typeref:typename:void	file:
stmmac_vid_crc32_le	stmmac_main.c	/^static u32 stmmac_vid_crc32_le(__le16 vid_le)$/;"	f	typeref:typename:u32	file:
stmmac_vlan_insert	stmmac_main.c	/^static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,$/;"	f	typeref:typename:bool	file:
stmmac_vlan_rx_add_vid	stmmac_main.c	/^static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)$/;"	f	typeref:typename:int	file:
stmmac_vlan_rx_kill_vid	stmmac_main.c	/^static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)$/;"	f	typeref:typename:int	file:
stmmac_vlan_update	stmmac_main.c	/^static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)$/;"	f	typeref:typename:int	file:
stmmac_xgmac2_c22_format	stmmac_mdio.c	/^static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,$/;"	f	typeref:typename:int	file:
stmmac_xgmac2_c45_format	stmmac_mdio.c	/^static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,$/;"	f	typeref:typename:int	file:
stmmac_xgmac2_mdio_read	stmmac_mdio.c	/^static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)$/;"	f	typeref:typename:int	file:
stmmac_xgmac2_mdio_write	stmmac_mdio.c	/^static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,$/;"	f	typeref:typename:int	file:
stmmac_xmit	stmmac_main.c	/^static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)$/;"	f	typeref:typename:netdev_tx_t	file:
stmmac_xpcs_config	hwif.h	/^#define stmmac_xpcs_config(/;"	d
stmmac_xpcs_get_state	hwif.h	/^#define stmmac_xpcs_get_state(/;"	d
stmmac_xpcs_link_up	hwif.h	/^#define stmmac_xpcs_link_up(/;"	d
stmmac_xpcs_probe	hwif.h	/^#define stmmac_xpcs_probe(/;"	d
stmmac_xpcs_validate	hwif.h	/^#define stmmac_xpcs_validate(/;"	d
stmmachdr	stmmac_selftests.c	/^struct stmmachdr {$/;"	s	file:
stop_rx	hwif.h	/^	void (*stop_rx)(void __iomem *ioaddr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan)
stop_tx	hwif.h	/^	void (*stop_tx)(void __iomem *ioaddr, u32 chan);$/;"	m	struct:stmmac_dma_ops	typeref:typename:void (*)(void __iomem * ioaddr,u32 chan)
sub_second_inc	stmmac.h	/^	u32 sub_second_inc;$/;"	m	struct:stmmac_priv	typeref:typename:u32
sun7i_dwmac_driver	dwmac-sunxi.c	/^static struct platform_driver sun7i_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
sun7i_dwmac_match	dwmac-sunxi.c	/^static const struct of_device_id sun7i_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
sun7i_fix_speed	dwmac-sunxi.c	/^static void sun7i_fix_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
sun7i_gmac_exit	dwmac-sunxi.c	/^static void sun7i_gmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
sun7i_gmac_init	dwmac-sunxi.c	/^static int sun7i_gmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
sun7i_gmac_probe	dwmac-sunxi.c	/^static int sun7i_gmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
sun8i_ccu_reg_field	dwmac-sun8i.c	/^static const struct reg_field sun8i_ccu_reg_field = {$/;"	v	typeref:typename:const struct reg_field	file:
sun8i_dwmac_core_init	dwmac-sun8i.c	/^static void sun8i_dwmac_core_init(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_disable_dma_irq	dwmac-sun8i.c	/^static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_init	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_init(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_init_rx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_init_tx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_interrupt	dwmac-sun8i.c	/^static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,$/;"	f	typeref:typename:int	file:
sun8i_dwmac_dma_operation_mode_rx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_operation_mode_tx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_ops	dwmac-sun8i.c	/^static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {$/;"	v	typeref:typename:const struct stmmac_dma_ops	file:
sun8i_dwmac_dma_reset	dwmac-sun8i.c	/^static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_dma_start_rx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_start_tx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_stop_rx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dma_stop_tx	dwmac-sun8i.c	/^static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_driver	dwmac-sun8i.c	/^static struct platform_driver sun8i_dwmac_driver = {$/;"	v	typeref:struct:platform_driver	file:
sun8i_dwmac_dump_mac_regs	dwmac-sun8i.c	/^static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_dump_regs	dwmac-sun8i.c	/^static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_enable_dma_irq	dwmac-sun8i.c	/^static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_enable_dma_transmission	dwmac-sun8i.c	/^static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_exit	dwmac-sun8i.c	/^static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_flow_ctrl	dwmac-sun8i.c	/^static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_get_syscon_from_dev	dwmac-sun8i.c	/^static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)$/;"	f	typeref:struct:regmap *	file:
sun8i_dwmac_get_umac_addr	dwmac-sun8i.c	/^static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_init	dwmac-sun8i.c	/^static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_match	dwmac-sun8i.c	/^static const struct of_device_id sun8i_dwmac_match[] = {$/;"	v	typeref:typename:const struct of_device_id[]	file:
sun8i_dwmac_ops	dwmac-sun8i.c	/^static const struct stmmac_ops sun8i_dwmac_ops = {$/;"	v	typeref:typename:const struct stmmac_ops	file:
sun8i_dwmac_power_internal_phy	dwmac-sun8i.c	/^static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_probe	dwmac-sun8i.c	/^static int sun8i_dwmac_probe(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_register_mdio_mux	dwmac-sun8i.c	/^static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_remove	dwmac-sun8i.c	/^static int sun8i_dwmac_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_reset	dwmac-sun8i.c	/^static int sun8i_dwmac_reset(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_rx_ipc_enable	dwmac-sun8i.c	/^static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_set_filter	dwmac-sun8i.c	/^static void sun8i_dwmac_set_filter(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_set_mac	dwmac-sun8i.c	/^static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_set_mac_loopback	dwmac-sun8i.c	/^static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)$/;"	f	typeref:typename:void	file:
sun8i_dwmac_set_syscon	dwmac-sun8i.c	/^static int sun8i_dwmac_set_syscon(struct device *dev,$/;"	f	typeref:typename:int	file:
sun8i_dwmac_set_umac_addr	dwmac-sun8i.c	/^static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,$/;"	f	typeref:typename:void	file:
sun8i_dwmac_setup	dwmac-sun8i.c	/^static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)$/;"	f	typeref:struct:mac_device_info *	file:
sun8i_dwmac_unpower_internal_phy	dwmac-sun8i.c	/^static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)$/;"	f	typeref:typename:int	file:
sun8i_dwmac_unset_syscon	dwmac-sun8i.c	/^static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)$/;"	f	typeref:typename:void	file:
sun8i_syscon_reg_field	dwmac-sun8i.c	/^static const struct reg_field sun8i_syscon_reg_field = {$/;"	v	typeref:typename:const struct reg_field	file:
sunxi_priv_data	dwmac-sun8i.c	/^struct sunxi_priv_data {$/;"	s	file:
sunxi_priv_data	dwmac-sunxi.c	/^struct sunxi_priv_data {$/;"	s	file:
support_mii	dwmac-sun8i.c	/^	bool support_mii;$/;"	m	struct:emac_variant	typeref:typename:bool	file:
support_rgmii	dwmac-sun8i.c	/^	bool support_rgmii;$/;"	m	struct:emac_variant	typeref:typename:bool	file:
support_rmii	dwmac-sun8i.c	/^	bool support_rmii;$/;"	m	struct:emac_variant	typeref:typename:bool	file:
suspend	dwmac-stm32.c	/^	int (*suspend)(struct stm32_dwmac *dwmac);$/;"	m	struct:stm32_ops	typeref:typename:int (*)(struct stm32_dwmac * dwmac)	file:
suspended	dwmac-rk.c	/^	bool suspended;$/;"	m	struct:rk_priv_data	typeref:typename:bool	file:
synopsys_id	stmmac.h	/^	int synopsys_id;$/;"	m	struct:stmmac_priv	typeref:typename:int
sys_mgr_base_addr	dwmac-socfpga.c	/^	struct regmap *sys_mgr_base_addr;$/;"	m	struct:socfpga_dwmac	typeref:struct:regmap *	file:
syscfg_clk	dwmac-stm32.c	/^	struct clk *syscfg_clk;$/;"	m	struct:stm32_dwmac	typeref:struct:clk *	file:
syscfg_eth_mask	dwmac-stm32.c	/^	u32 syscfg_eth_mask;$/;"	m	struct:stm32_ops	typeref:typename:u32	file:
syscon_field	dwmac-sun8i.c	/^	const struct reg_field *syscon_field;$/;"	m	struct:emac_variant	typeref:typename:const struct reg_field *	file:
sysfs_display_ring	stmmac_main.c	/^static void sysfs_display_ring(void *head, int size, int extend_desc,$/;"	f	typeref:typename:void	file:
systime_flags	stmmac.h	/^	u32 systime_flags;$/;"	m	struct:stmmac_priv	typeref:typename:u32
table	stmmac.h	/^	u32 table[STMMAC_RSS_MAX_TABLE_SIZE];$/;"	m	struct:stmmac_rss	typeref:typename:u32[]
table_pos	stmmac.h	/^	unsigned int table_pos;$/;"	m	struct:stmmac_tc_entry	typeref:typename:unsigned int
tbs	stmmac.h	/^	int tbs;$/;"	m	struct:stmmac_tx_queue	typeref:typename:int
tbssel	common.h	/^	unsigned int tbssel;$/;"	m	struct:dma_features	typeref:typename:unsigned int
tc	common.h	/^	const struct stmmac_tc_ops *tc;$/;"	m	struct:mac_device_info	typeref:typename:const struct stmmac_tc_ops *
tc	hwif.c	/^	const void *tc;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:const void *	file:
tc	stmmac_main.c	/^static int tc = TC_DEFAULT;$/;"	v	typeref:typename:int	file:
tc_add_basic_flow	stmmac_tc.c	/^static int tc_add_basic_flow(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_add_flow	stmmac_tc.c	/^static int tc_add_flow(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_add_ip4_flow	stmmac_tc.c	/^static int tc_add_ip4_flow(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_add_ports_flow	stmmac_tc.c	/^static int tc_add_ports_flow(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_config_knode	stmmac_tc.c	/^static int tc_config_knode(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_del_flow	stmmac_tc.c	/^static int tc_del_flow(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_delete_knode	stmmac_tc.c	/^static int tc_delete_knode(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_entries	stmmac.h	/^	struct stmmac_tc_entry *tc_entries;$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_tc_entry *
tc_entries_max	stmmac.h	/^	unsigned int tc_entries_max;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
tc_fill_actions	stmmac_tc.c	/^static int tc_fill_actions(struct stmmac_tc_entry *entry,$/;"	f	typeref:typename:int	file:
tc_fill_all_pass_entry	stmmac_tc.c	/^static void tc_fill_all_pass_entry(struct stmmac_tc_entry *entry)$/;"	f	typeref:typename:void	file:
tc_fill_entry	stmmac_tc.c	/^static int tc_fill_entry(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_find_entry	stmmac_tc.c	/^static struct stmmac_tc_entry *tc_find_entry(struct stmmac_priv *priv,$/;"	f	typeref:struct:stmmac_tc_entry *	file:
tc_find_flow	stmmac_tc.c	/^static struct stmmac_flow_entry *tc_find_flow(struct stmmac_priv *priv,$/;"	f	typeref:struct:stmmac_flow_entry *	file:
tc_flow_parsers	stmmac_tc.c	/^} tc_flow_parsers[] = {$/;"	v	typeref:struct:__anonf294d2f10108[]
tc_init	stmmac_tc.c	/^static int tc_init(struct stmmac_priv *priv)$/;"	f	typeref:typename:int	file:
tc_off_max	stmmac.h	/^	unsigned int tc_off_max;$/;"	m	struct:stmmac_priv	typeref:typename:unsigned int
tc_parse_flow_actions	stmmac_tc.c	/^static int tc_parse_flow_actions(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_setup_cbs	stmmac_tc.c	/^static int tc_setup_cbs(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_setup_cls	stmmac_tc.c	/^static int tc_setup_cls(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_setup_cls_u32	stmmac_tc.c	/^static int tc_setup_cls_u32(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_setup_etf	stmmac_tc.c	/^static int tc_setup_etf(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_setup_taprio	stmmac_tc.c	/^static int tc_setup_taprio(struct stmmac_priv *priv,$/;"	f	typeref:typename:int	file:
tc_unfill_entry	stmmac_tc.c	/^static void tc_unfill_entry(struct stmmac_priv *priv,$/;"	f	typeref:typename:void	file:
tcp	stmmac_selftests.c	/^	int tcp;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
tegra_eqos	dwmac-dwc-qos-eth.c	/^struct tegra_eqos {$/;"	s	file:
tegra_eqos_data	dwmac-dwc-qos-eth.c	/^static const struct dwc_eth_dwmac_data tegra_eqos_data = {$/;"	v	typeref:typename:const struct dwc_eth_dwmac_data	file:
tegra_eqos_fix_speed	dwmac-dwc-qos-eth.c	/^static void tegra_eqos_fix_speed(void *priv, unsigned int speed)$/;"	f	typeref:typename:void	file:
tegra_eqos_init	dwmac-dwc-qos-eth.c	/^static int tegra_eqos_init(struct platform_device *pdev, void *priv)$/;"	f	typeref:typename:int	file:
tegra_eqos_probe	dwmac-dwc-qos-eth.c	/^static void *tegra_eqos_probe(struct platform_device *pdev,$/;"	f	typeref:typename:void *	file:
tegra_eqos_remove	dwmac-dwc-qos-eth.c	/^static int tegra_eqos_remove(struct platform_device *pdev)$/;"	f	typeref:typename:int	file:
tgl_common_data	dwmac-intel.c	/^static int tgl_common_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
tgl_sgmii1g_info	dwmac-intel.c	/^static struct stmmac_pci_info tgl_sgmii1g_info = {$/;"	v	typeref:struct:stmmac_pci_info	file:
tgl_sgmii_data	dwmac-intel.c	/^static int tgl_sgmii_data(struct pci_dev *pdev,$/;"	f	typeref:typename:int	file:
threshold	common.h	/^	unsigned long threshold;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
time_stamp	common.h	/^	unsigned int time_stamp;$/;"	m	struct:dma_features	typeref:typename:unsigned int
time_stamp_irq	dwmac4.h	/^	time_stamp_irq = 0x00001000,$/;"	e	enum:dwmac4_irq_status
timeout	stmmac_selftests.c	/^	int timeout;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
timestamp	stmmac_selftests.c	/^	u64 timestamp;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:u64	file:
timestamp_dropped	common.h	/^	unsigned long timestamp_dropped;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
timing_adj_clk	dwmac-meson8b.c	/^	struct clk			*timing_adj_clk;$/;"	m	struct:meson8b_dwmac	typeref:struct:clk *	file:
triple_ratio	dwmac1000.h	/^	triple_ratio = 0x00008000,	\/* 3:1 *\/$/;"	e	enum:rx_tx_priority_ratio
tse_pcs	altr_tse_pcs.h	/^struct tse_pcs {$/;"	s
tse_pcs_base	altr_tse_pcs.h	/^	void __iomem *tse_pcs_base;$/;"	m	struct:tse_pcs	typeref:typename:void __iomem *
tse_pcs_fix_mac_speed	altr_tse_pcs.c	/^void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,$/;"	f	typeref:typename:void
tse_pcs_init	altr_tse_pcs.c	/^int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs)$/;"	f	typeref:typename:int
tse_pcs_reset	altr_tse_pcs.c	/^static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs)$/;"	f	typeref:typename:int	file:
tso	stmmac.h	/^	bool tso;$/;"	m	struct:stmmac_priv	typeref:typename:bool
tsoen	common.h	/^	unsigned int tsoen;$/;"	m	struct:dma_features	typeref:typename:unsigned int
tstamp_config	stmmac.h	/^	struct hwtstamp_config tstamp_config;$/;"	m	struct:stmmac_priv	typeref:struct:hwtstamp_config
ttc_control	dwmac100.h	/^enum ttc_control {$/;"	g
ttc_control	dwmac1000.h	/^enum ttc_control {$/;"	g
tx_carrier	common.h	/^	unsigned long tx_carrier;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_clean	common.h	/^	unsigned long tx_clean;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_clk	dwmac-intel-plat.c	/^	struct clk *tx_clk;$/;"	m	struct:intel_dwmac	typeref:struct:clk *	file:
tx_clk	dwmac-sun8i.c	/^	struct clk *tx_clk;$/;"	m	struct:sunxi_priv_data	typeref:struct:clk *	file:
tx_clk	dwmac-sunxi.c	/^	struct clk *tx_clk;$/;"	m	struct:sunxi_priv_data	typeref:struct:clk *	file:
tx_clk_en	dwmac-intel-plat.c	/^	bool tx_clk_en;$/;"	m	struct:intel_dwmac_data	typeref:typename:bool	file:
tx_clk_rate	dwmac-intel-plat.c	/^	unsigned long tx_clk_rate;$/;"	m	struct:intel_dwmac_data	typeref:typename:unsigned long	file:
tx_coal_frames	stmmac.h	/^	u32 tx_coal_frames;$/;"	m	struct:stmmac_priv	typeref:typename:u32
tx_coal_timer	stmmac.h	/^	u32 tx_coal_timer;$/;"	m	struct:stmmac_priv	typeref:typename:u32
tx_coalesce	stmmac.h	/^	int tx_coalesce;$/;"	m	struct:stmmac_priv	typeref:typename:int
tx_coe	common.h	/^	unsigned int tx_coe;$/;"	m	struct:dma_features	typeref:typename:unsigned int
tx_count_frames	stmmac.h	/^	u32 tx_count_frames;$/;"	m	struct:stmmac_tx_queue	typeref:typename:u32
tx_deferred	common.h	/^	unsigned long tx_deferred;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_delay	dwmac-mediatek.c	/^	u32 tx_delay;$/;"	m	struct:mac_delay_struct	typeref:typename:u32	file:
tx_delay	dwmac-rk.c	/^	int tx_delay;$/;"	m	struct:rk_priv_data	typeref:typename:int	file:
tx_delay_max	dwmac-mediatek.c	/^	u32 tx_delay_max;$/;"	m	struct:mediatek_dwmac_variant	typeref:typename:u32	file:
tx_delay_max	dwmac-sun8i.c	/^	u8 tx_delay_max;$/;"	m	struct:emac_variant	typeref:typename:u8	file:
tx_delay_ns	dwmac-meson8b.c	/^	u32				tx_delay_ns;$/;"	m	struct:meson8b_dwmac	typeref:typename:u32	file:
tx_dma_own	common.h	/^	tx_dma_own = 0x4,$/;"	e	enum:tx_frame_status
tx_done	common.h	/^	tx_done = 0x0,$/;"	e	enum:tx_frame_status
tx_early_irq	common.h	/^	unsigned long tx_early_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_err	common.h	/^	tx_err = 0x2,$/;"	e	enum:tx_frame_status
tx_fifo_size	common.h	/^	unsigned int tx_fifo_size;$/;"	m	struct:dma_features	typeref:typename:unsigned int
tx_frame_flushed	common.h	/^	unsigned long tx_frame_flushed;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_frame_status	common.h	/^enum tx_frame_status {$/;"	g
tx_hard_error	common.h	/^	tx_hard_error = 0x1,$/;"	e	enum:dma_irq_status
tx_hard_error_bump_tc	common.h	/^	tx_hard_error_bump_tc = 0x2,$/;"	e	enum:dma_irq_status
tx_inv	dwmac-mediatek.c	/^	bool tx_inv;$/;"	m	struct:mac_delay_struct	typeref:typename:bool	file:
tx_ip_header_error	common.h	/^	unsigned long tx_ip_header_error;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_jabber	common.h	/^	unsigned long tx_jabber;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_jabber_irq	common.h	/^	unsigned long tx_jabber_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_losscarrier	common.h	/^	unsigned long tx_losscarrier;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_lpi_enabled	stmmac.h	/^	int tx_lpi_enabled;$/;"	m	struct:stmmac_priv	typeref:typename:int
tx_lpi_timer	stmmac.h	/^	int tx_lpi_timer;$/;"	m	struct:stmmac_priv	typeref:typename:int
tx_normal_irq_n	common.h	/^	unsigned long tx_normal_irq_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_not_ls	common.h	/^	tx_not_ls = 0x1,$/;"	e	enum:tx_frame_status
tx_path_in_lpi_mode	stmmac.h	/^	bool tx_path_in_lpi_mode;$/;"	m	struct:stmmac_priv	typeref:typename:bool
tx_payload_error	common.h	/^	unsigned long tx_payload_error;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_pkt_n	common.h	/^	unsigned long tx_pkt_n;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_process_stopped_irq	common.h	/^	unsigned long tx_process_stopped_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_queue	stmmac.h	/^	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];$/;"	m	struct:stmmac_priv	typeref:struct:stmmac_tx_queue[]
tx_queue_prio	hwif.h	/^	void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 prio,u32 queue)
tx_retime_src	dwmac-sti.c	/^	u32 tx_retime_src;	\/* TXCLK Retiming*\/$/;"	m	struct:sti_dwmac	typeref:typename:u32	file:
tx_set_ic_bit	common.h	/^	unsigned long tx_set_ic_bit;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_skbuff	stmmac.h	/^	struct sk_buff **tx_skbuff;$/;"	m	struct:stmmac_tx_queue	typeref:struct:sk_buff **
tx_skbuff_dma	stmmac.h	/^	struct stmmac_tx_info *tx_skbuff_dma;$/;"	m	struct:stmmac_tx_queue	typeref:struct:stmmac_tx_info *
tx_status	hwif.h	/^	int (*tx_status)(void *data, struct stmmac_extra_stats *x,$/;"	m	struct:stmmac_desc_ops	typeref:typename:int (*)(void * data,struct stmmac_extra_stats * x,struct dma_desc * p,void __iomem * ioaddr)
tx_tail_addr	stmmac.h	/^	u32 tx_tail_addr;$/;"	m	struct:stmmac_tx_queue	typeref:typename:u32
tx_tso_frames	common.h	/^	unsigned long tx_tso_frames;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_tso_nfrags	common.h	/^	unsigned long tx_tso_nfrags;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_undeflow_irq	common.h	/^	unsigned long tx_undeflow_irq;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
tx_vlan	common.h	/^	unsigned long tx_vlan;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
txtimer	stmmac.h	/^	struct timer_list txtimer;$/;"	m	struct:stmmac_tx_queue	typeref:struct:timer_list
unicast_filter_entries	common.h	/^	unsigned int unicast_filter_entries;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
update_vlan_hash	hwif.h	/^	void (*update_vlan_hash)(struct mac_device_info *hw, u32 hash,$/;"	m	struct:stmmac_ops	typeref:typename:void (*)(struct mac_device_info * hw,u32 hash,__le16 perfect_match,bool is_double)
use_internal_phy	dwmac-sun8i.c	/^	bool use_internal_phy;$/;"	m	struct:sunxi_priv_data	typeref:typename:bool	file:
use_riwt	stmmac.h	/^	int use_riwt;$/;"	m	struct:stmmac_priv	typeref:typename:int
val	stmmac.h	/^	} __packed val;$/;"	m	struct:stmmac_tc_entry	typeref:struct:stmmac_tc_entry::__anon84d70a400208 __packed
valid	dwmac5.c	/^	bool valid;$/;"	m	struct:dwmac5_error_desc	typeref:typename:bool	file:
valid	dwxgmac2_core.c	/^	bool valid;$/;"	m	struct:dwxgmac3_error_desc	typeref:typename:bool	file:
value	dwmac-qcom-ethqos.c	/^	unsigned int value;$/;"	m	struct:ethqos_emac_por	typeref:typename:unsigned int	file:
variant	dwmac-mediatek.c	/^	const struct mediatek_dwmac_variant *variant;$/;"	m	struct:mediatek_dwmac_plat_data	typeref:typename:const struct mediatek_dwmac_variant *	file:
variant	dwmac-sun8i.c	/^	const struct emac_variant *variant;$/;"	m	struct:sunxi_priv_data	typeref:typename:const struct emac_variant *	file:
version	stmmac_selftests.c	/^	__be32 version;$/;"	m	struct:stmmachdr	typeref:typename:__be32	file:
vlan	stmmac_selftests.c	/^	int vlan;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
vlan_fail_q	common.h	/^	u8 vlan_fail_q;$/;"	m	struct:mac_device_info	typeref:typename:u8
vlan_fail_q_en	common.h	/^	bool vlan_fail_q_en;$/;"	m	struct:mac_device_info	typeref:typename:bool
vlan_filter	common.h	/^	u32 vlan_filter[32];$/;"	m	struct:mac_device_info	typeref:typename:u32[32]
vlan_id	stmmac_selftests.c	/^	int vlan_id;$/;"	m	struct:stmmac_test_priv	typeref:typename:int	file:
vlan_id_in	stmmac_selftests.c	/^	int vlan_id_in;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
vlan_id_out	stmmac_selftests.c	/^	int vlan_id_out;$/;"	m	struct:stmmac_packet_attrs	typeref:typename:int	file:
vlan_tag	common.h	/^	unsigned long vlan_tag;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
vlan_tag_priority_val	common.h	/^	unsigned long vlan_tag_priority_val;$/;"	m	struct:stmmac_extra_stats	typeref:typename:unsigned long
vlhash	common.h	/^	unsigned int vlhash;$/;"	m	struct:dma_features	typeref:typename:unsigned int
vlins	common.h	/^	unsigned int vlins;$/;"	m	struct:dma_features	typeref:typename:unsigned int
wake_up_frame_en	dwmac1000.h	/^	wake_up_frame_en = 0x00000004,$/;"	e	enum:power_event
wake_up_frame_en	dwmac4.h	/^	wake_up_frame_en = 0x00000004,$/;"	e	enum:power_event
wake_up_rx_frame	dwmac1000.h	/^	wake_up_rx_frame = 0x00000040,$/;"	e	enum:power_event
wake_up_rx_frame	dwmac4.h	/^	wake_up_rx_frame = 0x00000040,$/;"	e	enum:power_event
watchdog	stmmac_main.c	/^static int watchdog = TX_TIMEO;$/;"	v	typeref:typename:int	file:
wol_irq	stmmac.h	/^	int wol_irq;$/;"	m	struct:stmmac_priv	typeref:typename:int
wol_irq	stmmac.h	/^	int wol_irq;$/;"	m	struct:stmmac_resources	typeref:typename:int
wolopts	stmmac.h	/^	int wolopts;$/;"	m	struct:stmmac_priv	typeref:typename:int
wq	stmmac.h	/^	struct workqueue_struct *wq;$/;"	m	struct:stmmac_priv	typeref:struct:workqueue_struct *
xgmac	hwif.c	/^	bool xgmac;$/;"	m	struct:stmmac_hwif_entry	typeref:typename:bool	file:
xgmii	common.h	/^	} xgmii;$/;"	m	struct:mac_link	typeref:struct:mac_link::__anon3fde68840108
xlgmac	common.h	/^	unsigned int xlgmac;$/;"	m	struct:mac_device_info	typeref:typename:unsigned int
xlgmii	common.h	/^	} xlgmii;$/;"	m	struct:mac_link	typeref:struct:mac_link::__anon3fde68840208
xpcs	common.h	/^	const struct mdio_xpcs_ops *xpcs;$/;"	m	struct:mac_device_info	typeref:typename:const struct mdio_xpcs_ops *
xpcs_args	common.h	/^	struct mdio_xpcs_args xpcs_args;$/;"	m	struct:mac_device_info	typeref:struct:mdio_xpcs_args
